Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.1 (WebPack) - P.15xf Target Family: Spartan6
OS Platform: NT64 Target Device: xc6slx9
Project ID (random number) 71d62301d2f64f8fb1f74236c9306baf.BF22F45E83BB4B39BD3927D670A19C30.5 Target Package: tqg144
Registration ID __0_0_0 Target Speed: -2
Date Generated 2015-06-08T16:23:24 Tool Flow ISE
 
User Environment
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i7-3612QM CPU @ 2.10GHz CPU Speed 2095 MHz
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i7-3612QM CPU @ 2.10GHz CPU Speed 2095 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=2
  • 12-bit subtractor=2
 Comparators=26
  • 10-bit comparator greater=22
  • 11-bit comparator greater=4
 Counters=2
  • 11-bit up counter=2
 Multiplexers=58
  • 10-bit 2-to-1 multiplexer=11
  • 32-bit 2-to-1 multiplexer=47
 Registers=32
  • Flip-Flops=32
 		MiscellaneousStatistics
  • AGG_BONDED_IO=17
  • AGG_IO=17
  • AGG_LOCED_IO=17
  • AGG_SLICE=28
  • NUM_BONDED_IOB=17
  • NUM_BSFULL=32
  • NUM_BSLUTONLY=55
  • NUM_BSUSED=87
  • NUM_BUFG=2
  • NUM_BUFIO2=1
  • NUM_BUFIO2FB=1
  • NUM_DCM=1
  • NUM_LOCED_IOB=17
  • NUM_LOGIC_O5ANDO6=31
  • NUM_LOGIC_O5ONLY=1
  • NUM_LOGIC_O6ONLY=55
  • NUM_LUT_RT_O6=1
  • NUM_SLICEL=8
  • NUM_SLICEX=20
  • NUM_SLICE_CARRY4=6
  • NUM_SLICE_CONTROLSET=4
  • NUM_SLICE_CYINIT=119
  • NUM_SLICE_F7MUX=3
  • NUM_SLICE_FF=34
  • NUM_SLICE_UNUSEDCTRL=16
  • NUM_UNUSABLE_FF_BELS=22
 		NetStatistics
  • NumNets_Active=132
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEACROSS=3
  • NumNodesOfType_Active_BOUNCEIN=18
  • NumNodesOfType_Active_BUFGOUT=2
  • NumNodesOfType_Active_BUFHINP2OUT=2
  • NumNodesOfType_Active_BUFIOINP=2
  • NumNodesOfType_Active_CLKPIN=12
  • NumNodesOfType_Active_CLKPINFEED=10
  • NumNodesOfType_Active_CNTRLPIN=15
  • NumNodesOfType_Active_DOUBLE=137
  • NumNodesOfType_Active_GENERIC=27
  • NumNodesOfType_Active_GLOBAL=14
  • NumNodesOfType_Active_INPUT=8
  • NumNodesOfType_Active_IOBIN2OUT=19
  • NumNodesOfType_Active_IOBOUTPUT=19
  • NumNodesOfType_Active_LUTINPUT=410
  • NumNodesOfType_Active_OUTBOUND=111
  • NumNodesOfType_Active_OUTPUT=118
  • NumNodesOfType_Active_PADINPUT=14
  • NumNodesOfType_Active_PADOUTPUT=3
  • NumNodesOfType_Active_PINBOUNCE=47
  • NumNodesOfType_Active_PINFEED=453
  • NumNodesOfType_Active_PINFEED2=1
  • NumNodesOfType_Active_QUAD=39
  • NumNodesOfType_Active_REGINPUT=5
  • NumNodesOfType_Active_SINGLE=190
  • NumNodesOfType_Gnd_BOUNCEIN=3
  • NumNodesOfType_Gnd_CLKPIN=1
  • NumNodesOfType_Gnd_CNTRLPIN=2
  • NumNodesOfType_Gnd_HGNDOUT=3
  • NumNodesOfType_Gnd_OUTBOUND=1
  • NumNodesOfType_Gnd_OUTPUT=1
  • NumNodesOfType_Gnd_PINBOUNCE=4
  • NumNodesOfType_Gnd_PINFEED=3
  • NumNodesOfType_Gnd_REGINPUT=4
  • NumNodesOfType_Gnd_SINGLE=1
  • NumNodesOfType_Vcc_HVCCOUT=12
  • NumNodesOfType_Vcc_LUTINPUT=32
  • NumNodesOfType_Vcc_PINFEED=32
 SiteStatistics
  • BUFG-BUFGMUX=2
  • IOB-IOBM=8
  • IOB-IOBS=9
  • SLICEL-SLICEM=3
  • SLICEX-SLICEL=5
  • SLICEX-SLICEM=3
 		SiteSummary
  • BUFG=2
  • BUFG_BUFG=2
  • BUFIO2=1
  • BUFIO2FB=1
  • BUFIO2FB_BUFIO2FB=1
  • BUFIO2_BUFIO2=1
  • CARRY4=6
  • DCM=1
  • DCM_DCM=1
  • FF_SR=2
  • IOB=17
  • IOB_IMUX=3
  • IOB_INBUF=3
  • IOB_OUTBUF=14
  • LUT5=32
  • LUT6=87
  • PAD=17
  • REG_SR=32
  • SELMUX2_1=3
  • SLICEL=8
  • SLICEX=20
 
Configuration Data
BUFIO2FB_BUFIO2FB
  • DIVIDE_BYPASS=[TRUE:1]
  • INVERT_INPUTS=[FALSE:1]
 BUFIO2_BUFIO2
  • DIVIDE=[1:1]
  • DIVIDE_BYPASS=[TRUE:1]
  • I_INVERT=[FALSE:1]
 DCM
  • PSCLK=[PSCLK_INV:0] [PSCLK:1]
  • PSEN=[PSEN_INV:0] [PSEN:1]
  • PSINCDEC=[PSINCDEC:1] [PSINCDEC_INV:0]
  • RST=[RST:1] [RST_INV:0]
 DCM_DCM
  • CLKDV_DIVIDE=[2.0:1]
  • CLKIN_DIVIDE_BY_2=[FALSE:1]
  • CLKOUT_PHASE_SHIFT=[NONE:1]
  • CLK_FEEDBACK=[1X:1]
  • DESKEW_ADJUST=[5:1]
  • DFS_FREQUENCY_MODE=[LOW:1]
  • DLL_FREQUENCY_MODE=[LOW:1]
  • DSS_MODE=[NONE:1]
  • DUTY_CYCLE_CORRECTION=[TRUE:1]
  • PSCLK=[PSCLK_INV:0] [PSCLK:1]
  • PSEN=[PSEN_INV:0] [PSEN:1]
  • PSINCDEC=[PSINCDEC:1] [PSINCDEC_INV:0]
  • RST=[RST:1] [RST_INV:0]
  • STARTUP_WAIT=[FALSE:1]
  • VERY_HIGH_FREQUENCY=[FALSE:1]
 FF_SR
  • CK=[CK:2] [CK_INV:0]
  • SRINIT=[SRINIT0:2]
  • SYNC_ATTR=[ASYNC:2]
 IOB_OUTBUF
  • DRIVEATTRBOX=[12:14]
  • SLEW=[SLOW:14]
  • SUSPEND=[3STATE:14]
 REG_SR
  • CK=[CK:32] [CK_INV:0]
  • LATCH_OR_FF=[FF:32]
  • SRINIT=[SRINIT0:30] [SRINIT1:2]
  • SYNC_ATTR=[ASYNC:32]
 SLICEL
  • CLK=[CLK:6] [CLK_INV:0]
 SLICEX
  • CLK=[CLK:6] [CLK_INV:0]
 
Pin Data
BUFG
  • I0=2
  • O=2
 BUFG_BUFG
  • I0=2
  • O=2
 BUFIO2
  • DIVCLK=1
  • I=1
 BUFIO2FB
  • I=1
  • O=1
 BUFIO2FB_BUFIO2FB
  • I=1
  • O=1
 BUFIO2_BUFIO2
  • DIVCLK=1
  • I=1
 CARRY4
  • CIN=4
  • CO3=4
  • CYINIT=2
  • DI0=6
  • DI1=4
  • DI2=4
  • DI3=4
  • O0=6
  • O1=6
  • O2=4
  • O3=4
  • S0=6
  • S1=6
  • S2=4
  • S3=4
 DCM
  • CLK0=1
  • CLKDV=1
  • CLKFB=1
  • CLKIN=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
 DCM_DCM
  • CLK0=1
  • CLKDV=1
  • CLKFB=1
  • CLKIN=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
 FF_SR
  • CK=2
  • D=2
  • Q=2
  • SR=2
 IOB
  • I=3
  • O=14
  • PAD=17
 IOB_IMUX
  • I=3
  • OUT=3
 IOB_INBUF
  • OUT=3
  • PAD=3
 IOB_OUTBUF
  • IN=14
  • OUT=14
 LUT5
  • A1=9
  • A2=10
  • A3=18
  • A4=18
  • A5=11
  • O5=32
 LUT6
  • A1=46
  • A2=60
  • A3=65
  • A4=85
  • A5=87
  • A6=87
  • O6=87
 PAD
  • PAD=17
 REG_SR
  • CE=2
  • CK=32
  • D=32
  • Q=32
  • SR=32
 SELMUX2_1
  • 0=3
  • 1=3
  • OUT=3
  • S0=3
 SLICEL
  • A=2
  • A1=3
  • A2=3
  • A3=3
  • A4=7
  • A5=8
  • A6=8
  • AMUX=1
  • AQ=6
  • AX=3
  • B=2
  • B1=4
  • B2=4
  • B3=6
  • B4=8
  • B5=8
  • B6=8
  • BQ=6
  • BX=1
  • C1=3
  • C2=4
  • C3=5
  • C4=7
  • C5=7
  • C6=7
  • CIN=4
  • CLK=6
  • CMUX=2
  • COUT=4
  • CQ=5
  • CX=4
  • D=1
  • D1=4
  • D2=5
  • D3=6
  • D4=8
  • D5=8
  • D6=8
  • DQ=4
  • DX=1
  • SR=6
 SLICEX
  • A=12
  • A1=13
  • A2=16
  • A3=17
  • A4=17
  • A5=17
  • A6=17
  • AMUX=3
  • AQ=5
  • B=12
  • B1=9
  • B2=12
  • B3=13
  • B4=15
  • B5=15
  • B6=15
  • BMUX=4
  • BQ=3
  • C=11
  • C1=8
  • C2=12
  • C3=13
  • C4=13
  • C5=14
  • C6=14
  • CE=2
  • CLK=6
  • CMUX=4
  • CQ=3
  • D=10
  • D1=4
  • D2=6
  • D3=10
  • D4=10
  • D5=10
  • D6=10
  • DMUX=6
  • SR=6
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <ise_file> <fname>.ngd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <ise_file> <fname>.ngd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <ise_file> <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 48 34 0 0 0 0 0
bitgen 70 70 0 0 0 0 0
map 79 70 0 0 0 0 0
ngdbuild 83 83 0 0 0 0 0
par 70 70 0 0 0 0 0
trce 67 67 0 0 0 0 0
xst 83 84 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/ise_c_overview.htm ( 1 ) /doc/usenglish/isehelp/ise_c_project_archive.htm ( 1 )
/doc/usenglish/isehelp/ise_c_project_browser.htm ( 1 ) /doc/usenglish/isehelp/ise_c_project_copy.htm ( 1 )
/doc/usenglish/isehelp/ise_p_creating_a_new_source.htm ( 1 ) /doc/usenglish/isehelp/ise_p_creating_a_project.htm ( 1 )
/doc/usenglish/isehelp/ise_p_open_ise_example.htm ( 1 ) /doc/usenglish/isehelp/pim_c_overview.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2015-05-19T22:00:47
PROP_intWbtProjectID=BF22F45E83BB4B39BD3927D670A19C30 PROP_intWbtProjectIteration=5
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_lockPinsUcfFile=changed PROP_xilxBitgStart_IntDone=true
PROP_AutoTop=true PROP_DevFamily=Spartan6
PROP_DevDevice=xc6slx9 PROP_DevFamilyPMName=spartan6
PROP_DevPackage=tqg144 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-2 PROP_PreferredLanguage=Verilog
FILE_COREGEN=1 FILE_UCF=1
FILE_VERILOG=3
 
Core Statistics
Core Type=clk_wiz_v4_1
clkin1_period=20.0 clkin2_period=20.0 clock_mgr_type=AUTO feedback_source=FDBK_AUTO
feedback_type=SINGLE manual_override=false num_out_clk=1 primtype_sel=DCM_SP
use_clk_valid=false use_dyn_phase_shift=false use_dyn_reconfig=false use_freeze=false
use_inclk_stopped=false use_inclk_switchover=false use_locked=false use_max_i_jitter=false
use_min_o_jitter=false use_phase_alignment=true use_power_down=false use_reset=true
use_status=false
 
Unisim Statistics
XST_UNISIM_SUMMARY
XST_NUM_BUFG=1 XST_NUM_IBUFG=1
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=2 NGDBUILD_NUM_DCM_SP=1 NGDBUILD_NUM_FDC=32 NGDBUILD_NUM_FDPE=2
NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=2 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_LUT2=20
NGDBUILD_NUM_LUT3=11 NGDBUILD_NUM_LUT4=8 NGDBUILD_NUM_LUT5=27 NGDBUILD_NUM_LUT6=38
NGDBUILD_NUM_MUXCY=18 NGDBUILD_NUM_MUXF7=3 NGDBUILD_NUM_OBUF=14 NGDBUILD_NUM_XORCY=20
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=2 NGDBUILD_NUM_DCM_SP=1 NGDBUILD_NUM_FDC=32 NGDBUILD_NUM_FDPE=2
NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=2 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_LUT2=20
NGDBUILD_NUM_LUT3=11 NGDBUILD_NUM_LUT4=8 NGDBUILD_NUM_LUT5=27 NGDBUILD_NUM_LUT6=38
NGDBUILD_NUM_MUXCY=18 NGDBUILD_NUM_MUXF7=3 NGDBUILD_NUM_OBUF=14 NGDBUILD_NUM_XORCY=20
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc6slx9-2-tqg144
-top=<design_top> -opt_mode=Speed -opt_level=1 -power=NO
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -sd=<No customer specific name> -write_timing_constraints=NO
-cross_clock_analysis=NO -bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100
-dsp_utilization_ratio=100 -reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto
-safe_implementation=No -fsm_style=LUT -ram_extract=Yes -ram_style=Auto
-rom_extract=Yes -shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO
-resource_sharing=YES -async_to_sync=NO -use_dsp48=Auto -iobuf=YES
-max_fanout=100000 -bufg=16 -register_duplication=YES -register_balancing=No
-optimize_primitives=NO -use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto
-iob=Auto -equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5