UART_TXD_Example Project Status (06/08/2015 - 15:16:20)
Project File: UART_TXD_Example.xise Parser Errors: No Errors
Module Name: UART_TXD_Example Implementation State: Programming File Generated
Target Device: xc6slx9-2tqg144
  • Errors:
No Errors
Product Version:ISE 14.1
  • Warnings:
15 Warnings (11 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 37 11,440 1%  
    Number used as Flip Flops 37      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 39 5,720 1%  
    Number used as logic 39 5,720 1%  
        Number using O6 output only 33      
        Number using O5 output only 0      
        Number using O5 and O6 6      
        Number used as ROM 0      
    Number used as Memory 0 1,440 0%  
Number of occupied Slices 16 1,430 1%  
Nummber of MUXCYs used 0 2,860 0%  
Number of LUT Flip Flop pairs used 41      
    Number with an unused Flip Flop 10 41 24%  
    Number with an unused LUT 2 41 4%  
    Number of fully used LUT-FF pairs 29 41 70%  
    Number of unique control sets 3      
    Number of slice register sites lost
        to control set restrictions
11 11,440 1%  
Number of bonded IOBs 12 102 11%  
    Number of LOCed IOBs 12 12 100%  
Number of RAMB16BWERs 0 32 0%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 2 16 12%  
    Number used as BUFGs 2      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 0 200 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 200 0%  
Number of OLOGIC2/OSERDES2s 0 200 0%  
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 16 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 4.13      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon Jun 8 15:15:37 201505 Warnings (1 new)3 Infos (2 new)
Translation ReportCurrentMon Jun 8 15:15:43 2015000
Map ReportCurrentMon Jun 8 15:15:52 2015008 Infos (2 new)
Place and Route ReportCurrentMon Jun 8 15:15:59 2015010 Warnings (10 new)3 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentMon Jun 8 15:16:04 2015004 Infos (0 new)
Bitgen ReportCurrentMon Jun 8 15:16:12 2015000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentMon Jun 8 15:16:12 2015
WebTalk Log FileCurrentMon Jun 8 15:16:19 2015

Date Generated: 06/08/2015 - 15:16:20