Counter Project Status
Project File: Counter.xise Parser Errors: No Errors
Module Name: Counter Implementation State: Programming File Generated
Target Device: xc6slx9-2tqg144
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
3 Warnings (1 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 64 11,440 1%  
    Number used as Flip Flops 64      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 99 5,720 1%  
    Number used as logic 97 5,720 1%  
        Number using O6 output only 44      
        Number using O5 output only 39      
        Number using O5 and O6 14      
        Number used as ROM 0      
    Number used as Memory 0 1,440 0%  
    Number used exclusively as route-thrus 2      
        Number with same-slice register load 0      
        Number with same-slice carry load 2      
        Number with other load 0      
Number of occupied Slices 31 1,430 2%  
Nummber of MUXCYs used 48 2,860 1%  
Number of LUT Flip Flop pairs used 99      
    Number with an unused Flip Flop 42 99 42%  
    Number with an unused LUT 0 99 0%  
    Number of fully used LUT-FF pairs 57 99 57%  
    Number of unique control sets 5      
    Number of slice register sites lost
        to control set restrictions
16 11,440 1%  
Number of bonded IOBs 16 102 15%  
    Number of LOCed IOBs 16 16 100%  
Number of RAMB16BWERs 0 32 0%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 1 16 6%  
    Number used as BUFGs 1      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 0 200 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 200 0%  
Number of OLOGIC2/OSERDES2s 0 200 0%  
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 16 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.40      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon Jun 8 15:53:51 201503 Warnings (1 new)4 Infos (0 new)
Translation ReportCurrentMon Jun 8 15:53:57 2015000
Map ReportCurrentMon Jun 8 15:54:05 2015006 Infos (0 new)
Place and Route ReportCurrentMon Jun 8 15:54:12 2015003 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentMon Jun 8 15:54:17 2015004 Infos (0 new)
Bitgen ReportCurrentMon Jun 8 15:54:25 2015000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentMon Jun 8 15:54:25 2015
WebTalk Log FileCurrentMon Jun 8 15:54:33 2015

Date Generated: 12/23/2019 - 21:06:19