SW_SSEG Project Status
Project File: SSEG_Display.xise Parser Errors: No Errors
Module Name: SW_SSEG Implementation State: Programming File Generated
Target Device: xc6slx9-2tqg144
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
1 Warning (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 18 11,440 1%  
    Number used as Flip Flops 18      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 28 5,720 1%  
    Number used as logic 27 5,720 1%  
        Number using O6 output only 5      
        Number using O5 output only 16      
        Number using O5 and O6 6      
        Number used as ROM 0      
    Number used as Memory 0 1,440 0%  
    Number used exclusively as route-thrus 1      
        Number with same-slice register load 0      
        Number with same-slice carry load 1      
        Number with other load 0      
Number of occupied Slices 11 1,430 1%  
Nummber of MUXCYs used 20 2,860 1%  
Number of LUT Flip Flop pairs used 28      
    Number with an unused Flip Flop 10 28 35%  
    Number with an unused LUT 0 28 0%  
    Number of fully used LUT-FF pairs 18 28 64%  
    Number of unique control sets 1      
    Number of slice register sites lost
        to control set restrictions
6 11,440 1%  
Number of bonded IOBs 24 102 23%  
    Number of LOCed IOBs 24 24 100%  
Number of RAMB16BWERs 0 32 0%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 1 16 6%  
    Number used as BUFGs 1      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 0 200 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 200 0%  
Number of OLOGIC2/OSERDES2s 0 200 0%  
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 16 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 1.87      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon Jun 8 15:28:37 201501 Warning (0 new)2 Infos (2 new)
Translation ReportCurrentMon Jun 8 15:28:43 2015000
Map ReportCurrentMon Jun 8 15:28:50 2015006 Infos (0 new)
Place and Route ReportCurrentMon Jun 8 15:28:57 2015003 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentMon Jun 8 15:29:02 2015004 Infos (0 new)
Bitgen ReportCurrentMon Jun 8 15:29:10 2015000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentMon Jun 8 15:29:10 2015
WebTalk Log FileCurrentMon Jun 8 15:29:18 2015

Date Generated: 12/23/2019 - 21:02:46