Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.1 (WebPack) - P.15xf Target Family: Spartan6
OS Platform: NT64 Target Device: xc6slx9
Project ID (random number) 71d62301d2f64f8fb1f74236c9306baf.519B2F5CEA4649EFAE31AA9CD11C1457.5 Target Package: tqg144
Registration ID __0_0_0 Target Speed: -2
Date Generated 2015-06-08T12:33:06 Tool Flow ISE
 
User Environment
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i7-3612QM CPU @ 2.10GHz CPU Speed 2095 MHz
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i7-3612QM CPU @ 2.10GHz CPU Speed 2095 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=1
  • 21-bit subtractor=1
 FSMs=1 Multiplexers=7
  • 1-bit 2-to-1 multiplexer=2
  • 21-bit 2-to-1 multiplexer=4
  • 21-bit 4-to-1 multiplexer=1
 Registers=21
  • Flip-Flops=21
 		MiscellaneousStatistics
  • AGG_BONDED_IO=5
  • AGG_IO=5
  • AGG_LOCED_IO=4
  • AGG_SLICE=15
  • NUM_BONDED_IOB=5
  • NUM_BSFULL=23
  • NUM_BSLUTONLY=26
  • NUM_BSUSED=49
  • NUM_BUFG=1
  • NUM_LOCED_IOB=4
  • NUM_LOGIC_O5ANDO6=19
  • NUM_LOGIC_O5ONLY=1
  • NUM_LOGIC_O6ONLY=29
  • NUM_LUT_RT_O6=1
  • NUM_SLICEL=6
  • NUM_SLICEX=9
  • NUM_SLICE_CARRY4=6
  • NUM_SLICE_CONTROLSET=1
  • NUM_SLICE_CYINIT=70
  • NUM_SLICE_FF=23
  • NUM_SLICE_UNUSEDCTRL=8
  • NUM_UNUSABLE_FF_BELS=1
 		NetStatistics
  • NumNets_Active=64
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEACROSS=5
  • NumNodesOfType_Active_BOUNCEIN=13
  • NumNodesOfType_Active_BUFGOUT=1
  • NumNodesOfType_Active_BUFHINP2OUT=1
  • NumNodesOfType_Active_CLKPIN=7
  • NumNodesOfType_Active_CLKPINFEED=1
  • NumNodesOfType_Active_CNTRLPIN=7
  • NumNodesOfType_Active_DOUBLE=42
  • NumNodesOfType_Active_GENERIC=7
  • NumNodesOfType_Active_GLOBAL=9
  • NumNodesOfType_Active_INPUT=6
  • NumNodesOfType_Active_IOBIN2OUT=4
  • NumNodesOfType_Active_IOBOUTPUT=4
  • NumNodesOfType_Active_LUTINPUT=165
  • NumNodesOfType_Active_OUTBOUND=54
  • NumNodesOfType_Active_OUTPUT=56
  • NumNodesOfType_Active_PADINPUT=2
  • NumNodesOfType_Active_PADOUTPUT=3
  • NumNodesOfType_Active_PINBOUNCE=27
  • NumNodesOfType_Active_PINFEED=182
  • NumNodesOfType_Active_QUAD=21
  • NumNodesOfType_Active_REGINPUT=1
  • NumNodesOfType_Active_SINGLE=66
  • NumNodesOfType_Vcc_HVCCOUT=5
  • NumNodesOfType_Vcc_LUTINPUT=20
  • NumNodesOfType_Vcc_PINFEED=20
 SiteStatistics
  • BUFG-BUFGMUX=1
  • IOB-IOBM=2
  • IOB-IOBS=3
  • SLICEL-SLICEM=6
  • SLICEX-SLICEL=3
 		SiteSummary
  • BUFG=1
  • BUFG_BUFG=1
  • CARRY4=6
  • HARD1=1
  • IOB=5
  • IOB_IMUX=3
  • IOB_INBUF=3
  • IOB_OUTBUF=2
  • LUT5=20
  • LUT6=49
  • PAD=5
  • REG_SR=23
  • SLICEL=6
  • SLICEX=9
 
Configuration Data
IOB_OUTBUF
  • DRIVEATTRBOX=[12:2]
  • SLEW=[SLOW:2]
  • SUSPEND=[3STATE:2]
 REG_SR
  • CK=[CK:23] [CK_INV:0]
  • LATCH_OR_FF=[FF:23]
  • SRINIT=[SRINIT0:23]
  • SYNC_ATTR=[ASYNC:23]
 SLICEX
  • CLK=[CLK:7] [CLK_INV:0]
 
Pin Data
BUFG
  • I0=1
  • O=1
 BUFG_BUFG
  • I0=1
  • O=1
 CARRY4
  • CIN=5
  • CO3=5
  • CYINIT=1
  • DI0=5
  • DI1=5
  • DI2=5
  • DI3=5
  • O0=6
  • O1=5
  • O2=5
  • O3=5
  • S0=6
  • S1=5
  • S2=5
  • S3=5
 HARD1
  • 1=1
 IOB
  • I=3
  • O=2
  • PAD=5
 IOB_IMUX
  • I=3
  • OUT=3
 IOB_INBUF
  • OUT=3
  • PAD=3
 IOB_OUTBUF
  • IN=2
  • OUT=2
 LUT5
  • O5=20
 LUT6
  • A1=5
  • A2=27
  • A3=28
  • A4=28
  • A5=48
  • A6=49
  • O6=49
 PAD
  • PAD=5
 REG_SR
  • CK=23
  • D=23
  • Q=23
  • SR=23
 SLICEL
  • A5=5
  • A6=6
  • AMUX=6
  • B5=5
  • B6=5
  • BMUX=5
  • C5=5
  • C6=5
  • CIN=5
  • CMUX=5
  • COUT=5
  • D5=5
  • D6=5
  • DMUX=5
 SLICEX
  • A=2
  • A1=3
  • A2=9
  • A3=9
  • A4=9
  • A5=9
  • A6=9
  • AQ=7
  • B=2
  • B1=1
  • B2=6
  • B3=7
  • B4=7
  • B5=7
  • B6=7
  • BQ=6
  • BX=1
  • C=1
  • C2=6
  • C3=6
  • C4=6
  • C5=6
  • C6=6
  • CLK=7
  • CQ=5
  • D=1
  • D1=1
  • D2=6
  • D3=6
  • D4=6
  • D5=6
  • D6=6
  • DQ=5
  • SR=7
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <ise_file> <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 42 29 0 0 0 0 0
bitgen 49 49 0 0 0 0 0
map 56 49 0 0 0 0 0
ngdbuild 56 56 0 0 0 0 0
par 49 49 0 0 0 0 0
trce 46 46 0 0 0 0 0
xst 59 60 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/ise_c_overview.htm ( 1 ) /doc/usenglish/isehelp/ise_c_project_archive.htm ( 1 )
/doc/usenglish/isehelp/ise_c_project_browser.htm ( 1 ) /doc/usenglish/isehelp/ise_c_project_copy.htm ( 1 )
/doc/usenglish/isehelp/ise_p_creating_a_new_source.htm ( 1 ) /doc/usenglish/isehelp/ise_p_creating_a_project.htm ( 1 )
/doc/usenglish/isehelp/ise_p_open_ise_example.htm ( 1 ) /doc/usenglish/isehelp/pim_c_overview.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2015-05-30T18:04:43
PROP_intWbtProjectID=519B2F5CEA4649EFAE31AA9CD11C1457 PROP_intWbtProjectIteration=5
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_lockPinsUcfFile=changed PROP_xilxBitgStart_IntDone=true
PROP_AutoTop=true PROP_DevFamily=Spartan6
PROP_ibiswriterOutputFile=btn PROP_DevDevice=xc6slx9
PROP_DevFamilyPMName=spartan6 PROP_DevPackage=tqg144
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-2
PROP_PreferredLanguage=Verilog PROP_netgenPostMapSimModelName=btn_map.v
PROP_netgenPostParSimModelName=btn_timesim.v PROP_netgenPostSynthesisSimModelName=btn_synthesis.v
PROP_netgenPostXlateSimModelName=btn_translate.v FILE_UCF=1
FILE_VERILOG=1
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FDC=23 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=2
NGDBUILD_NUM_INV=20 NGDBUILD_NUM_LUT1=1 NGDBUILD_NUM_LUT4=1 NGDBUILD_NUM_LUT5=22
NGDBUILD_NUM_LUT6=5 NGDBUILD_NUM_MUXCY=20 NGDBUILD_NUM_OBUF=2 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=21
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FDC=23 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=2
NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=20 NGDBUILD_NUM_LUT1=1 NGDBUILD_NUM_LUT4=1
NGDBUILD_NUM_LUT5=22 NGDBUILD_NUM_LUT6=5 NGDBUILD_NUM_MUXCY=20 NGDBUILD_NUM_OBUF=2
NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=21
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc6slx9-2-tqg144
-top=<design_top> -opt_mode=Speed -opt_level=1 -power=NO
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -dsp_utilization_ratio=100
-reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No
-fsm_style=LUT -ram_extract=Yes -ram_style=Auto -rom_extract=Yes
-shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES
-async_to_sync=NO -use_dsp48=Auto -iobuf=YES -max_fanout=100000
-bufg=16 -register_duplication=YES -register_balancing=No -optimize_primitives=NO
-use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto -iob=Auto
-equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5