 
cpldfit:  version P.20131013                        Xilinx Inc.
                                  Fitter Report
Design Name: first                               Date: 12-11-2019, 10:42PM
Device Used: XC9536-7-PC44
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
1  /36  (  3%) 1   /180  (  1%) 1  /72  (  1%)   0  /36  (  0%) 2  /34  (  6%)

** Function Block Resources **

Function    Mcells      FB Inps     Signals     Pterms      IO          
Block       Used/Tot    Used/Tot    Used        Used/Tot    Used/Tot    
FB1           0/18        0/36        0           0/90       0/17
FB2           1/18        1/36        1           1/90       1/17
             -----       -----                   -----       -----     
              1/36        1/72                    1/180      1/34 

* - Resource is exhausted

** Global Control Resources **

Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    1           1    |  I/O              :     2      28
Output        :    1           1    |  GCK/IO           :     0       3
Bidirectional :    0           0    |  GTS/IO           :     0       2
GCK           :    0           0    |  GSR/IO           :     0       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total      2           2

** Power Data **

There are 1 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
   use the default filename of 'first.ise'.
*************************  Summary of Mapped Logic  ************************

** 1 Outputs **

Signal              Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                Pts   Inps          No.  Type    Use     Mode Rate State
led                 1     1     FB2_1   1    I/O     O       STD  FAST 

** 1 Inputs **

Signal              Loc     Pin  Pin     Pin     
Name                        No.  Type    Use     
button              FB1_1   2    I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@)         - Signal used as input (wire-AND input) to the macrocell logic.
               The number of Signals Used may exceed the number of FB Inputs
               Used due to wire-ANDing in the switch matrix.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               0/36
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB1_1   2     I/O     I
(unused)              0       0     0   5     FB1_2   3     I/O     
(unused)              0       0     0   5     FB1_3   5     GCK/I/O 
(unused)              0       0     0   5     FB1_4   4     I/O     
(unused)              0       0     0   5     FB1_5   6     GCK/I/O 
(unused)              0       0     0   5     FB1_6   8     I/O     
(unused)              0       0     0   5     FB1_7   7     GCK/I/O 
(unused)              0       0     0   5     FB1_8   9     I/O     
(unused)              0       0     0   5     FB1_9   11    I/O     
(unused)              0       0     0   5     FB1_10  12    I/O     
(unused)              0       0     0   5     FB1_11  13    I/O     
(unused)              0       0     0   5     FB1_12  14    I/O     
(unused)              0       0     0   5     FB1_13  18    I/O     
(unused)              0       0     0   5     FB1_14  19    I/O     
(unused)              0       0     0   5     FB1_15  20    I/O     
(unused)              0       0     0   5     FB1_16  22    I/O     
(unused)              0       0     0   5     FB1_17  24    I/O     
(unused)              0       0     0   5     FB1_18        (b)     
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               1/35
Number of signals used by logic mapping into function block:  1
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
led                   1       0     0   4     FB2_1   1     I/O     O
(unused)              0       0     0   5     FB2_2   44    I/O     
(unused)              0       0     0   5     FB2_3   42    GTS/I/O 
(unused)              0       0     0   5     FB2_4   43    I/O     
(unused)              0       0     0   5     FB2_5   40    GTS/I/O 
(unused)              0       0     0   5     FB2_6   39    GSR/I/O 
(unused)              0       0     0   5     FB2_7   38    I/O     
(unused)              0       0     0   5     FB2_8   37    I/O     
(unused)              0       0     0   5     FB2_9   36    I/O     
(unused)              0       0     0   5     FB2_10  35    I/O     
(unused)              0       0     0   5     FB2_11  34    I/O     
(unused)              0       0     0   5     FB2_12  33    I/O     
(unused)              0       0     0   5     FB2_13  29    I/O     
(unused)              0       0     0   5     FB2_14  28    I/O     
(unused)              0       0     0   5     FB2_15  27    I/O     
(unused)              0       0     0   5     FB2_16  26    I/O     
(unused)              0       0     0   5     FB2_17  25    I/O     
(unused)              0       0     0   5     FB2_18        (b)     

Signals Used by Logic in Function Block
  1: button           

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
led                  X....................................... 1       1
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********


led <= button;

Register Legend:
 FDCPE (Q,D,C,CLR,PRE); 
 FTCPE (Q,D,C,CLR,PRE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC9536-7-PC44


   --------------------------------  
  /6  5  4  3  2  1  44 43 42 41 40 \
 | 7                             39 | 
 | 8                             38 | 
 | 9                             37 | 
 | 10                            36 | 
 | 11         XC9536-7-PC44      35 | 
 | 12                            34 | 
 | 13                            33 | 
 | 14                            32 | 
 | 15                            31 | 
 | 16                            30 | 
 | 17                            29 | 
 \ 18 19 20 21 22 23 24 25 26 27 28 /
   --------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 led                              23 GND                           
  2 button                           24 TIE                           
  3 TIE                              25 TIE                           
  4 TIE                              26 TIE                           
  5 TIE                              27 TIE                           
  6 TIE                              28 TIE                           
  7 TIE                              29 TIE                           
  8 TIE                              30 TDO                           
  9 TIE                              31 GND                           
 10 GND                              32 VCC                           
 11 TIE                              33 TIE                           
 12 TIE                              34 TIE                           
 13 TIE                              35 TIE                           
 14 TIE                              36 TIE                           
 15 TDI                              37 TIE                           
 16 TMS                              38 TIE                           
 17 TCK                              39 TIE                           
 18 TIE                              40 TIE                           
 19 TIE                              41 VCC                           
 20 TIE                              42 TIE                           
 21 VCC                              43 TIE                           
 22 TIE                              44 TIE                           


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc9536-7-PC44
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
FASTConnect/UIM optimzation                 : ON
Local Feedback                              : ON
Pin Feedback                                : ON
Input Limit                                 : 36
Pterm Limit                                 : 25
