#robotics Logs

May 01 2019

12:39 AM orlock: Nuugh
04:26 AM BitEvil is now known as SpeedEvil
03:15 PM Mattx: How is this acting as a signal scaler? I'm assuming the signal is out of scale (ie, 0-12v) to be used by an arduino (0-5v), and somehow this fixes the problem, but how? https://i.imgur.com/O3oqSg9.png
03:16 PM polprog: the name youre looking for is level converter
03:16 PM polprog: and that opamp is configured as a voltage follower
03:17 PM polprog: which means that the voltage on the output is the same as the voltage on the + input
03:17 PM Mattx: yeah, that's why it's confusing, the opamp is not scaling the signal
03:17 PM Mattx: so what is?
03:17 PM polprog: can you paste some bigger part of the schem?
03:17 PM Mattx: sure, one sec
03:18 PM Mattx: http://onloop.net/hairyplotter/images/final_eog_ckt.png
03:18 PM polprog: that resistor divider looks like its biasing thesignal at between agnd and V-
03:18 PM Mattx: it's right where it says "scaler"
03:19 PM polprog: hmm in this case it might be a signal scaler
03:19 PM polprog: since its analog signals, not digital
03:20 PM polprog: looking at the bigger picture it looks like IC5 is just an output buffer
03:20 PM Mattx: how do you think it works then? the voltage divider biases it and brings it a little bit down, but it has to be the correct amplitude beforehand right?
03:20 PM polprog: nope
03:20 PM polprog: looks at J1
03:20 PM polprog: look at*
03:21 PM polprog: if its in the position 1-2 then the voltage divider doesnt do anything, the buffer is connected to IC2B
03:21 PM Mattx: j1 is just a jumper to disable the previous opamp
03:21 PM polprog: yeah
03:22 PM polprog: so if IC2B is disabled then the divider biases it at half the negative voltage
03:23 PM polprog: i think the scaler part was supposed to be both IC5 and IC2B since its the only one with adjustable gain, or any gain at all
03:23 PM polprog: well, any non-1 gain
03:23 PM polprog: why is agnd at +5 V
03:24 PM Mattx: so wait, if J1 is in 2-3 (ie IC2B is disabled), then the vol divider biases the input and then IC5 just follows its input. fine
03:24 PM polprog: yeah so the voltrage conevrsion for the arduino is just done by not letting the output signal reach outside 0-5 V range since thats the supply range of IC5
03:25 PM polprog: if J1 is in 2-3, then the divider forces 2.5 V at the output (via the buffer amp) when the input signal is zero
03:25 PM Mattx: if J1 is in 1-2, both opamps are active and you can scale the signal by adjusting the gain of IC2B
03:25 PM polprog: yes
03:25 PM Mattx: if it's outside the range of IC5, it'll clip and you're safe
03:25 PM polprog: its not the most elegant way to do so but yes
03:26 PM polprog: what is this thing?
03:26 PM polprog: horiz and vertical, 50hz notch filter, 16hz lpf
03:26 PM polprog: some analog sensor interface?
03:26 PM Mattx: it's https://en.wikipedia.org/wiki/Electrooculography
03:26 PM polprog: hmm
03:27 PM polprog: i can see why the 50hz filter is there, okay
03:27 PM polprog: eyeball scope
03:27 PM Mattx: correct
03:27 PM Mattx: polprog, what are more elegant ways of doing this or any of the rest?
03:28 PM polprog: the simplest would be to use some diodes connected at gnd and 5V
03:29 PM polprog: there are internal preotection diodes inside the opamp but they arent really meant to be clipping all the time so if you happen to clip often then some external ones would be nice
03:29 PM Mattx: a diode to clip the signal? I have to see that circuit, one sec
03:30 PM polprog: apart from that i would connect pin 2 to pin 3 on the potentiometer in IC2B (and IC7B) since its a precision circuit and that unconnected pin could pick up noise that you have filtered previously
03:31 PM polprog: also mains indcued noise is not pure 50Hz, it has harmonics and other noises so its not easy to filter out
03:31 PM polprog: audio people have been dealing with this for ages
03:32 PM polprog: going back to that pot, connecting two pins like that on a pot, making it a rheostat, is very common practice
03:32 PM Mattx: what do they do? a notch filter + LPF at let's say 20Hz is not enough??
03:33 PM polprog: hmm maybe in this case its enough
03:33 PM Mattx: I'm looking for a schematic of the diode solution to scale a signal, if you know how it's called...
03:34 PM polprog: pretction diode or diode limiter
03:34 PM Mattx: excellent
03:35 PM Mattx: another way would be to pass the signal through a voltage divider like in SIG--[R]--OUT--[R]--GND
03:36 PM polprog: no
03:37 PM polprog: that will basically divide your signal by some amount
03:37 PM Mattx: you are not guaranteed it wont' go above 5V but you can adjust the resistors if you know the signal
03:37 PM polprog: depending on the output impedance of your source
03:37 PM polprog: thats a bad idea
03:37 PM polprog: diode limiter is way better
03:37 PM polprog: you need two diodes like this
03:37 PM polprog: sec
03:38 PM polprog: hmm cant find a simple circuit using regular or schottky diodes
03:38 PM polprog: but a zener diode limiter will be pretty simple
03:39 PM polprog: http://hyperphysics.phy-astr.gsu.edu/hbase/Electronic/ietron/zenlim.gif like the top one here
03:40 PM Mattx: http://vlab.amrita.edu/userfiles/4/image/image(DiodeLimiter_case)/f1.png
03:40 PM polprog: no, this will limit between + and - 0.7 V
03:42 PM Mattx: I'm checking your image, I've no idea how that works as expected
03:42 PM polprog: http://tinyurl.com/y5qx4rxj
03:42 PM polprog: zener diode in here has a breakdown voltage of 5.6
03:43 PM polprog: when the input signal is below 0V, the diode is biased forward = works like a normal diode and forces -0.7 V (its forward voltage drop) on the output
03:43 PM polprog: if the input signal is in range of 0-5.6V the diode is not conducting = as if it wasnt there
03:44 PM polprog: if the input signal exceeds 5.6 V the diode will start conducting in the reverse direction (zener diodes do that safely) and force the output to be at 5.6V
03:45 PM Mattx: oh, it's not "any diode". makes sense
03:45 PM polprog: well any diode would work as well but the circuit that would limit between two chosen voltages is a little more compilcated
03:47 PM Mattx: I'm simulating the circuit I initially linked, it's working well but the voltage divider is not biasing the signal, weird
03:48 PM polprog: do you need it to bias the signal as well?
03:48 PM Mattx: http://onloop.net/hairyplotter/images/final_eog_ckt.png
03:48 PM Mattx: R16 and R7 there
03:48 PM polprog: yeah
03:48 PM Mattx: that should bring the signal down
03:48 PM polprog: no
03:48 PM Mattx: but it's not doing anything as far as I see
03:48 PM polprog: its a huge resistance - 11 megs
03:49 PM polprog: it doesnt have enough "force" to always bias the signal
03:49 PM polprog: lemme draw another simulation
03:49 PM Mattx: I'm using 1k for both R in my simulation
03:51 PM Mattx: https://i.imgur.com/eE3QzhJ.png
03:51 PM Mattx: the signal is clipped as expected but it's not centered at the midpoint between GND and V-
03:51 PM polprog: if you have a signal connected, even though those dc rmoval caps, theres enough current to neglect the biasing
03:52 PM polprog: http://tinyurl.com/yxdrzqaj
03:52 PM polprog: take a look here
03:52 PM Mattx: let me see
03:53 PM polprog: cange the values around
03:53 PM polprog: change*
03:54 PM polprog: tink about the 1k resistor as a source with a 1k output impedance (its really more complicated due to that cap, but lets pretend its not) and the voltage divider as a source with a 500k output impedance (two 1M conencted to two ideal voltage sources - 5V and 0V - in paralell)
03:54 PM polprog: wha tdo you think will have more influence on the output signal? the 1k source or the 500k source?
03:55 PM polprog: the 500k has 500 times less influence
03:55 PM polprog: so to speak
04:02 PM Mattx: polprog, without the diode your circuit doesn't bias the signal either. I have to bring the resistors to 500 to see a change
04:02 PM polprog: thats what i said
04:03 PM Mattx: right, I'm just confirming
04:03 PM Mattx: I'll simulate the original circuit again with different Rs, sec
04:04 PM polprog: try to simulate it with like a 1M in series with the cap
04:04 PM polprog: and use a smaller signal source
04:04 PM polprog: like 1V peak to peak max
04:04 PM polprog: then you will see the biasing in action
04:05 PM Mattx: the cap would be what? C6 in the circuit I'm studying?
04:06 PM Mattx: C6 and R6 I guess? I thought that was for DC removal
04:06 PM polprog: yes
04:06 PM Mattx: and R6 part of a LPF
04:06 PM Mattx: with the cap at its right
04:06 PM polprog: there are more than one LPFs there
04:07 PM polprog: basically C6 is the bias removal cap
04:07 PM polprog: R6 and C8 are the LPF
04:07 PM Mattx: oh ok, so I was right in that
04:07 PM polprog: so youd want a small signal source conencted to the left of C6
04:08 PM polprog: in fact a circuit where you have a cap conencted to the middle of a voltage divide both biases a signal at the divider voltage and is a highpass filter
04:09 PM polprog: in your case there is an opamp between the cap and the divider so its not the case. but its a circuit that you often seen in audio inputs
04:24 PM Mattx: polprog, https://i.imgur.com/wp0PSZg.png
04:24 PM Mattx: this is my circuit except for R32
04:24 PM Mattx: which I added
04:24 PM Mattx: "added bias" is at the same voltage as "added cap"
04:25 PM Mattx: ie, the voltage divider is not adding anything
04:25 PM Mattx: but after the voltage follower at the end, it does
04:25 PM polprog: what is the output impedance of the opamp in the simulation
04:26 PM Mattx: one sec, second day with the simulation, don't know how to check
04:26 PM Mattx: simulator *
04:26 PM polprog: if its zero then your divider wont do anything
04:27 PM Mattx: ah, you mean of U7 not U8?
04:27 PM polprog: add a 1k or 100R in series with the U7 output
04:27 PM polprog: yeah
04:27 PM Mattx: ok ok, got it, I'll check that
04:28 PM Mattx: you're right, that was the issue
04:28 PM Mattx: I wonder though why after passing by the second opamp it fixed the problem
04:28 PM polprog: what'sthus program by the way? labview?
04:28 PM veverak: deshipu: got my ego hyped up
04:28 PM Mattx: polprog, it's ltspice
04:28 PM veverak: deshipu: https://scontent-prg1-1.xx.fbcdn.net/v/t1.15752-9/s2048x2048/59659538_421824188594704_5216992651559043072_n.jpg?_nc_cat=103&_nc_ht=scontent-prg1-1.xx&oh=62d5bda41d16023766b33db86af3d9be&oe=5D755501
04:28 PM veverak: deshipu: autonomous cars
04:29 PM veverak: :)
04:29 PM polprog: you didnt fix the problem, its just the red trace is entirely covered by the blue one
04:29 PM durrf: woah
04:30 PM Mattx: so the original schematic is wrong, the 11M resistors are too high and it's missing a resistor at the opamp output as I just added
04:30 PM polprog: not really
04:30 PM polprog: or rather
04:30 PM polprog: move the biasing resistors before IC2B
04:30 PM polprog: if you want them to bias even when IC2B is active
04:32 PM Mattx: if I move the resistor before IC2B it won't bias, that was how I had it previously (https://i.imgur.com/wp0PSZg.png)
04:32 PM polprog: no, move the divider before IC2B
04:32 PM Mattx: ah, the whole divider
04:33 PM polprog: or add a resistor at the output of IC2B
04:33 PM Mattx: ok
04:33 PM polprog: but after pin 1 of the pot
04:33 PM polprog: otherwise youll have to recalculate the gtain
04:33 PM polprog: gain
04:34 PM polprog: https://i.imgur.com/0F22SbL.png
04:35 PM polprog: for example
04:35 PM Mattx: that definitely fixes the problem, I already tested it
04:35 PM Mattx: my point is without that added resistor the original circuit won't bias the signal
04:36 PM Mattx: if the opamp is active of course
04:36 PM Mattx: if it's disabled it will
04:37 PM Mattx: ie, J1 in 1-2, and the signal is not bias, UNLESS you add that resistor you just draw
04:37 PM Mattx: biased*
04:38 PM Mattx: jumper J1 in 2-3 and it works just fine, assuming the 11M resistors in the voltage divider are small enough to bias the signal
04:38 PM polprog: also reconsider if you need 11M resistors there
04:38 PM Mattx: that's my understanding as for now
04:38 PM polprog: resistances that big have quite a thermal noise
04:39 PM polprog: https://en.wikipedia.org/wiki/Johnson%E2%80%93Nyquist_noise
04:41 PM Mattx: you helped me quite a lot, thank you polprog
04:41 PM polprog: you're welcome
04:41 PM polprog: ;)
04:49 PM polprog: nighters
08:47 PM rue_mohr: :)