#robotics Logs

Jul 11 2018

12:06 AM rue_shop4: hmm, how do I make a voltage divider, where only one resistor is adjusted, but the output is lienar
12:10 AM rue_shop4: use a current source
12:10 AM rue_shop4: oh DUH, thanks...
12:10 AM rue_shop4: damnit, I want to make that phase discriminator today
12:12 AM rue_shop4: so mrdata there is another thing that I didn't try
12:12 AM rue_shop4: the oscillator that I made is based on a schmitt trigger
12:12 AM mrdata: ok
12:12 AM rue_shop4: I'v done varrying the capacitance, resistance, and inductance of the circuit
12:13 AM rue_shop4: all standard things, but I didn't do one that biases the levels of the shcmidtt to trip it sooner
12:14 AM rue_shop4: I'm also intereted in the results of doing digital pulse mixing with an (and?) gate
12:14 AM rue_shop4: dunno how that would get filtered
12:14 AM rue_shop4: iirc AND is the technical multiply
12:14 AM rue_shop4: or is it xor...
12:14 AM rue_shop4: na AND
12:15 AM mrdata: to solve thermal drift, operate the circuit in an oven so you can control temperature
12:15 AM rue_shop4: 0*1 = 0 1*0 = 0 0*0 = 0 1*1=1
12:15 AM rue_shop4: heh, 270c? :)
12:15 AM mrdata: not that high
12:15 AM rue_shop4: IT KEEPS FAILING!
12:15 AM mrdata: but 40C maybe
12:15 AM rue_shop4: .. and its dripping solder
12:15 AM mrdata: 50C possibly
12:17 AM rue_shop4: I'm reading on pll, wow, did things ever change since school
12:17 AM mrdata: 60C i doubt, but i would probably believe if someone told me
12:17 AM rue_shop4: the whole 2.4G thing completely revolutionized pll tech
12:18 AM rue_shop4: turns out that digital delay lines like the one that I did this osc with are key to all the new stuff
12:18 AM mrdata: how does that work
12:18 AM rue_shop4: ring oscillators made of voltage controlled delay cells
12:19 AM rue_shop4: generating multiphase signals
12:19 AM mrdata: how's that digital
12:19 AM rue_shop4: the thought train I used was
12:20 AM rue_shop4: you know how an edge detector is made
12:20 AM rue_shop4: xor with a RC?
12:20 AM rue_shop4: well, the RC is a delay
12:20 AM mrdata: yes
12:20 AM mrdata: tau = RC
12:20 AM rue_shop4: so, if I used that between schmitt inverters in a loop, I would be spreading the loop state switch over the delays
12:21 AM mrdata: tau is the time for the rise or fall by a factor of e
12:21 AM rue_shop4: so, to get 10:1 over, say 2, cells, I'd only need 5:1 on each cell
12:21 AM rue_shop4: cool?
12:21 AM rue_shop4: I was going to do an 8 unit delay loop with, say a 74244, but realized that I didn't need to break it down that much
12:22 AM rue_shop4: another cool thing is that, say for the 2 unit ring osc, you can xor the output from the two cells and you get double the ring freq
12:22 AM rue_shop4: aka with 8 cells, you can get 8x the ring freq
12:22 AM rue_shop4: (messy xor structure)
12:23 AM mrdata: um
12:23 AM rue_shop4: sorry, I might have run that too fast
12:24 AM mrdata: so for 2 cells, how do you control them
12:28 AM rue_shop4: right now, to get the 1Mhz-10Mhz, I have a {2x{1-10k,20pf rc -> inverter } inverter }
12:28 AM rue_shop4: well, I used a 2 gang 10k pot :)
12:28 AM zhanx: rue school me
12:28 AM mrdata: ganged, ok
12:28 AM zhanx: home made toner vs buying one
12:28 AM rue_shop4: I'm just hooking up two H11F1 optos
12:28 AM rue_shop4: home made toner!?!??! are you insane!?
12:28 AM rue_shop4: wait filament?
12:28 AM zhanx: figure i would ask no wire finder
12:28 AM rue_shop4: mrdata, so yea, those two delays in series, inverted and wrapped
12:28 AM mrdata: good
12:28 AM rue_shop4: I have a dds module that has good resolution between, say 100-1000Hz, do I'm pondering using it as a pll
12:28 AM rue_shop4: ref
12:28 AM rue_shop4: how to make a project complicated
12:29 AM zhanx: no but i am done with the soldering iron now so i am going to have a beer now
12:29 AM zhanx: never drink and burn ones self
12:30 AM rue_shop4: heh
12:31 AM zhanx: these are digix tablets. 7" screens. 8 are "bad"
12:31 AM zhanx: 2 work so far
12:31 AM rue_shop4: I got some securrity cams, on inspection it LOOKS like two of the smt filter caps arcd over
12:33 AM zhanx: i got a Power board out of a 55" vizio from today the diodes failed hard.
12:33 AM zhanx: they refused to use a UPS also
12:36 AM rue_shop4: if I were a robot I would not have this burning flesh problem
12:37 AM * rue_shop4 shakes hand vigerously
12:37 AM zhanx: carpel tunnel?
12:54 AM rue_shop4: hot wire jabbed under my fingernail cause ... dont have 4 arms
12:55 AM rue_shop4: ok, using H11F1 optos to control the cell delay isn't going to work, they cant generate large resistances in a stable way
12:55 AM rue_shop4: OK
01:06 AM rue_: I can try led/CDS tommorow
01:06 AM rue_: dont knwo what range I can get out of that
01:08 AM rue_: hmm the cds I bought were advertized at 45-140k, so the range is there
01:09 AM rue_: I wonder what their capacitance looks like
08:56 AM rue_: http://www.hanssummers.com/varicap/varicapdiode.html
08:56 AM rue_: hmm
07:53 PM rue_shop4: the CDS cells work fine, white leds
07:53 PM rue_shop4: suppose I could have stuck two cds on one led... oh well
08:56 PM rue_shop3: ok, so now I have the CDS cells operated by a op-amp doing a current sink
08:57 PM rue_shop3: so, its a 0-1V vco
08:57 PM rue_shop3: 0-1V 1Mhz-10Mhz
08:57 PM rue_shop3: well, actually it'll dial down to 500Khz, not going there...
10:01 PM rue_shop3: :) now I just want to make a whole bunch of cds/led cells
10:41 PM rue_shop3: so, an OR gate is two diodes with their cathodes tied togethor
10:41 PM rue_shop3: the cool thing is, that a PNP bipolar transistor is also two diodes with the cathode tied togethor
10:50 PM z64555: well, yeah
11:47 PM rue_: ok, the pnp caused some current flow that didn't help, moving on
11:47 PM rue_: trinary
11:48 PM rue_: ok, so the phase thing
11:48 PM rue_: https://i.stack.imgur.com/HPbAo.gif
11:48 PM rue_: uses up/down outputs
11:48 PM rue_: I want to see about changing it to use a 3 state buffer
11:49 PM rue_: this is a simple logic problem
11:49 PM rue_: up | down || data | enable
11:49 PM rue_: --------------------------
11:51 PM rue_: so, data is up & /down
11:51 PM rue_: and enable is up (+) down
11:51 PM rue_: ok, that sucks
11:56 PM mrdata: ?
11:57 PM mrdata: rue_, i ran ltspice model of the digital delay oscillator; worked nice with 3 stages of 2n3904
11:57 PM rue_: xor isn't a simple one to cough up on a passive budget
11:57 PM rue_: have a screenshot?
11:58 PM rue_: its a neat twist eh?
11:58 PM mrdata: it is. no screenshot right now tho
11:58 PM mrdata: it was quirky to get it started in ltspice tho
11:58 PM mrdata: tended not to oscillate, until i got the biasing right
11:58 PM rue_: heh
11:59 PM rue_: I used 74HC14
11:59 PM mrdata: and even then i had to kick it
11:59 PM rue_: prolly the real-world noise sparks it up
11:59 PM mrdata: yes
11:59 PM rue_: did you catch the delay from the transistors?
11:59 PM mrdata: i added parasitic inductance; that helped
11:59 PM rue_: few ns?