#linuxcnc-devel Logs

Oct 24 2019

07:32 AM pcw_home: Is it possible that you have quite old firmware?
07:35 AM pcw_home: also is it possible that the RPI shifted its basic clock frequency?
09:21 AM skunkworks: pcw_home: i have min/max set to 1750 but I don't know.
09:22 AM skunkworks: I was trying to fine something that would track the cpu freqency
09:22 AM skunkworks: Could hal do that I wonder?
09:22 AM skunkworks: I have force turbo=1 and also set govener set to performace.
12:45 PM pcw_home: Might be interesting to track the average of motion.servo.last-period
12:47 PM pcw_home: I know the default DPLL tuning parameter was changed at one time to accommodate fast frequency shifts caused by network time updates
12:49 PM skunkworks: I updated the firmware and the thing stopped booting :) working on it.
12:51 PM pcw_home: I was going to say there a bug in the SPI driver, but you are using Ethernet AFAIKR
12:52 PM pcw_home: (the bug being that once you run the rpspi driver, mesaflash can no longer access the card via SPI)
12:52 PM skunkworks: wait - did you mean the mesa firmware of rpi4 firmware?
12:53 PM pcw_home: mesa firmware
12:53 PM skunkworks: if mesa - it is from a few months ago - you made me a special one with extra encoders and smart serial
12:53 PM skunkworks: I updated the rpi firmware ;P
12:54 PM pcw_home: OK thata new enough to have the integral term in the DPLL
12:54 PM pcw_home: Oops hope the RPI is easily recoverable...
12:54 PM skunkworks: I just don't understand that it doesn't look like the periods are way off..
12:55 PM skunkworks: it boots the stock raspian - just building agian. I was meaning to do that anyway
12:55 PM skunkworks: just chuggs along and then bam - following error
12:55 PM pcw_home: you can see that something very significant happened on the left side of the traces
12:56 PM skunkworks: heh - I wasn't seeing anything odd
12:58 PM skunkworks: Like - this http://electronicsam.com/images/greenmachine/2019-10-23-182058_1920x1080_scrot.png
12:58 PM pcw_home: 1 + 3/4 divisions, the phase error tracks a large average frequency shift
12:59 PM skunkworks: but the read time and servo thread time look really good?
01:00 PM pcw_home: Yeah I dont think its that, more like the timebase shifted
01:03 PM pcw_home: in your first plot you have nearly 200 usec of baseline shift like the servo thread changed frequency a few % or so
01:04 PM skunkworks: ok - I will see what I can see with the frequency...
01:04 PM pcw_home: it may be possible to tweak the DPLL parameters to follow the shift but its probably better to find out why its shifting in the first place
01:05 PM skunkworks: pretty easy to make it do it - either just wait - sometime it take an hour or more - or launch chromium
01:06 PM pcw_home: its really hard to get more than 10 usec of baseline shift on my test PC (and its apparent its caused by latencies, not servo thread average frequency shifts)
01:07 PM skunkworks: yah - the 8300's are rock solid.
01:09 PM skunkworks: I could have the 7i92 put out a square wave and scope it - I do have a decent dss now..
01:09 PM skunkworks: switched with the servo thread.
01:12 PM skunkworks: I found an interesting behavoir of the 8300's.. I set one up and ran the latency test (just servo thread) and the latency peaked at >20us... I though it should be way better as I remember it being <5us..
01:12 PM skunkworks: You have to run the base thread to get those low latencies..
01:13 PM skunkworks: (which isn't a problem - still good latency for a servo thread - just thought there was a problem with the computer
01:15 PM pcw_home: yeah probably cache filling issues
01:16 PM pcw_home: The servo thread latency also improves at higher servo thread rates
01:17 PM pcw_home: There's a DPLL pin that can be output (better than GPIO)
01:19 PM skunkworks: what pin is that (or how do I do that?)
01:20 PM pcw_home: I would need to build firmware (the DPLL has external sync in and out pins)
01:21 PM skunkworks: oh!
01:21 PM pcw_home: (normally not connected, intended for testing and syncing multiple cards)
01:21 PM skunkworks: I am using 7i92_mx3660_ssed.bit
01:21 PM skunkworks: that you sent me
01:23 PM pcw_home: It may be more trouble than its worth because I dont know if the driver supports the pins
01:23 PM pcw_home: Ill take a look if I have any free time today
01:23 PM skunkworks: no rush
01:24 PM pcw_home: just a frequency counter with a 10 second gate on a toggling pin might provide some info
01:27 PM pcw_home: on the second plot you could probably get rid of the following errors by setting the stepgen sample time to -100 usec or even -200 usec
01:27 PM pcw_home: (not going to help if the DPLL loses sync though like in the first plot)
01:29 PM skunkworks: I had been running setp hm2_[HOSTMOT2](BOARD).0.dpll.01.timer-us -100
01:29 PM skunkworks: and i think I had tried -200
01:29 PM skunkworks: but I can play some more
01:31 PM pcw_home: you could also set the DPLL to track a bit faster and have more range
01:31 PM pcw_home: bbl