#linuxcnc-devel Logs

Feb 11 2018

08:40 AM pcw_home: GPIO access might be a better way to access FPGA cards than SPI ( universally there , usually pretty fast )
10:12 AM rene-dev: pcw_mesa you mean bit banging them? I think fixing the spi drivers is the better option...
10:13 AM rene-dev: what arm boards do the spi hostmot baords work best with?
10:43 AM jepler: rene-dev: none
10:43 AM rene-dev: uh oh
10:43 AM rene-dev: why is that?
10:44 AM rene-dev: I saw 2 hm2 spi drivers in the code, but they seem to use the spi kernel drivers
10:44 AM jepler: there's one driver for /dev/spidev but that driver has good RT performance on zero known ARM SBCs
10:44 AM jepler: the other is for rpi only, and seems like a terrible hack. it might have OK RT performance though
10:46 AM rene-dev: I dont see how bitbanging can be better than a bad spi driver...
11:00 AM pcw_home: some RASPI clone boards dont have SPI and GPIO byte bangin is faster
11:01 AM pcw_home: so universal
11:04 AM pcw_home: the Odroid C2 for example has no SPI (and is reported to be a decent host for Ethernet connected Mesa cards so should be OK for byte banging )
11:06 AM pcw_home: I think the potato uses the same hardware ( but does have SPI ) but a GPIO interface that did byte banging should work with almost anything
11:08 AM pcw_home: The driver would like have to do some clone specific data byte munging because of the weird selection of GPIO bits
11:08 AM pcw_home: available on different hardware
11:09 AM pcw_home: if the new GPIO driver is OK for RT that would be a big leg up
11:35 AM rene-dev: yes, if there is no spi available its bad
11:35 AM rene-dev: but usually bitbanging has bad performance...
11:36 AM pcw_home: bitbangin yes bytebanging no
11:41 AM rene-dev: ah, I see
11:43 AM pcw_home: SPI clocks for write only can be 100 MHz or more but for reads unless you have special late read options in the SPI controller 40 MHz is close to tops
11:45 AM pcw_home: but its easy to do 5m bytes per second on most GPIO (as long as you have relatively efficient access to the hardware )
11:45 AM pcw_home: ( with a simple byte interface like EPP or similar )
11:47 AM pcw_home: main disadvantage is that it uses more pins ( but if you are connected to the complete GPIO connector thats a non issue )
12:14 PM rene-dev: yeah, but if you have more than one data pin, its not spi anymore ;D
12:15 PM pcw_home: well... a lot of new flash memories are SPIx4
12:18 PM rene-dev: yes...
12:19 PM rene-dev: so you are thinking of making a new hm2 transport over 1 byte spi style thing?
12:23 PM pcw_home: well I have a new FPGA/Breakout RASPI/RASPI-Clone daughterboard It should work with SPI but EPP should work also
12:24 PM pcw_home: (or some improved EPP like byte wide GPIO interface )
12:24 PM pcw_home: for universality
12:30 PM rene-dev: ah. anyway, I think ethernet is the only way to go...
12:32 PM pcw_home: like to support Odroid C2, Rock64, Libre Potato, RasPI, Asus Tinker (at least hardware wise) if possible
12:35 PM pcw_home: yeah, Ethernet is great, but looking for something that could be supplied as a complete working LinuxCNC system in the $200 range
12:35 PM pcw_home: including 24V I/O etc
12:37 PM pcw_home: just looking at whats needed to cover that particular niche
12:38 PM rene-dev: last time I tried linuxcnc on arm was when the first pi came out... I guess things are a lot better now?
12:38 PM pcw_home: thats the hope...
12:40 PM pcw_home: I know Issy is running it on a Odroid C2 (Ethernet) so that gives me some hope its a reasonable way to go
12:42 PM rene-dev: Im working on a way of making everything a lot cheaper
12:44 PM pcw_home: Final product cost is typically as much in assembly costs as part costs
12:45 PM pcw_home: unless you are make 10000 or more
12:46 PM rene-dev: I know ;D