#linuxcnc-devel | Logs for 2015-01-20

[00:34:27] <cmorley> mozmck: I would think if you initialized hal_glib.py from a c program you could. Or write a c equivalent. but it is not bin done AFAIK.
[08:29:20] <cradek> > I have gang tooling can you add support for it ... why not use tool offsets ... oh I didn't know about those thanks
[08:29:23] <cradek> :-)
[08:29:27] <cradek> some threads go fast
[10:07:59] <seb_kuzminsky> every once in a while a user goes away happy, that's nice :-)
[10:12:43] <skunkworks> I don't believe it... ;)
[10:14:16] <skunkworks> other than gene saying that the docs suck on explaining it.. ;)
[10:14:40] <seb_kuzminsky> well...
[10:15:25] <cradek> gene has never met a documentation he likes
[10:16:55] <cradek> although it does talk exclusively about "length" which is kind of out of date
[10:17:52] <skunkworks> I guess I never looked at the docs.. just the tool table.
[10:19:36] <archivist> there are tool types not covered in the current table
[10:42:59] <seb_kuzminsky> cradek: when i pushed just now i got this error:
[10:43:00] <seb_kuzminsky> remote: Transport error: 500 Can't connect to localhost:9999 (Invalid argument)
[10:43:03] <seb_kuzminsky> remote: Unable to relay message. All servers failed
[10:43:11] <seb_kuzminsky> the push went through, but kgb didn't announce it
[10:45:49] <seb_kuzminsky> the email went out
[11:09:49] <cradek> > I had a problem posting to event Got_Request of session SOAPServer for DIR handler '.*'
[11:10:08] <cradek> kgb reports this error in some language I don't speak
[11:11:13] * cradek kicks KGB-linuxcnc in the SOAPServer
[11:29:03] <Roguish> pcw_home: hey, I got the fpga changed on a 5i20. everything shows ok in lspci and mesaflash. but get an error 'invalid cookie, is xxxx, should be yyyy' when loading hm2. what's up?
[11:30:53] <kwallace> Has anyone had trouble with gtksourceview and a line "<!-- interface-requires gtksourceview 0.0 -->" in the Glade file? With my setup with libgtksourceview2.0, when I open a glade file, Glade weeds out the requires comment and removes the sourceview widget. When I save the file, these bit are now missing and running the application barfs. I changed the requires to 2.0 and now Glade is happy and the sourceview survives. I'm just wondering where
[11:32:48] <pcw_home> Roguish: hmm, probably an open or short (the xxxx and yyyy are good hints where if you have a schematic)
[11:34:27] <Roguish> ok, i have the actual error message. how do i decode the xxxx and yyyy? do you mean schematic of the board? it errors with no cables attached.
[11:47:39] <pcw_home> I can look at the schematic of you have the xxxx (but if xxxx is 0x00000100 or 0xFFFFFFFF its will be tougher)
[11:48:23] <pcw_home> i would look under a microscope at the FPGA soldering
[11:51:29] <Roguish> ok. 0x558ACAFE expected 0x55AACAFE
[11:52:08] <pcw_home> OK a single bit error
[11:53:09] <Roguish> yeah, i have some microscope work to do on my other 5i20. it does not boot yet and i can see a couple of buggers on the fpga leads. so i will be back at my friend's shop down off Regatta blvd to use his miroscope and metcal.
[11:53:21] <pcw_home> bit 21 open probably
[11:53:51] <pcw_home> pretty sure this is on the bottom edge of the FPGA
[11:56:50] <Roguish> how do you determine it's bit 21? in case it changes as I work on the board..... I would like to be able to track the problem.
[11:57:41] <pcw_home> 0x558ACAFE xor 0x55AACAFE = 0x00200000
[11:58:09] <kwallace> Ah ha, Glade inserts the requires 0.0 line when a sourceview widget is added to the file from the pallet.
[11:59:11] <pcw_home> = 0b00000000001000000000000000000000
[12:01:02] <Roguish> and how does that map to the fpga?
[12:03:40] <pcw_home> you need the schematic to get the FPGA pins, let me see if theres a copy online
[12:05:16] <pcw_home> freeby.mesanet.com/5i20sch.zip
[12:11:01] <Roguish> got it. looking at schematic. how do I find the correct pin?
[12:13:11] <pcw_home> look at the FPGA page and find data bit 21
[12:13:30] <pcw_home> not sure what its named but it ends in 21
[12:14:04] <pcw_home> maybe LAD21
[12:17:20] <Roguish> yes, there is an LAD21. goes to pin 149. are the pins numbered around cw or ccw on the fpga?
[12:18:24] <Roguish> the fpga is on the board with pin 1 in the upper right corner looking at the board with the pci fingers on the bottom.
[12:19:28] <pcw_home> google ds001.pdf
[12:20:20] <Roguish> spartan ii datasheet, dated jume 13, 2008
[12:20:56] <pcw_home> oops may that one doesn't have the pictures
[12:26:47] <Roguish> found a pinout table.
[12:34:45] <Roguish> ok, found an image of the PQ208 packag.
[13:03:16] <Roguish> pcw_home: could it be IO21, not LAD21 ? or LAD22? the 1` is in position 22 of the binary number.
[13:03:47] <pcw_home> IO is GPIO so not the issue
[13:04:30] <pcw_home> 22nd position is bit 21
[13:04:41] <pcw_home> (bits start at 0)
[13:17:48] <Roguish> pcw_home: ok. got my sharpest probes, best magnifying glass and a bright light, and it seems the pin 149 is open.
[13:19:51] <cradek> I'd look at the rest of them too...
[13:21:35] <Roguish> gonna try and put a finer point on the probes. really need a microscope !!!! damn getting old sucks.
[13:21:47] <cradek> better than not getting old
[13:22:15] <Roguish> yeah, that's the way i look at it too. not quite ready for the dirt nap.
[13:22:46] <cradek> <- has a good microscope
[13:59:47] <Roguish> pcw_home: FIXED IT. loads properly. THANKS. gotta bet a microscope, finer probes, and finer iron tip.
[14:14:50] <skunkworks> was it a short?
[15:18:36] <skunkworks> Can you run glade as stand alone like pyvcp?
[15:19:01] <skunkworks> Gladevcp
[16:03:43] <kwallace> skunkworks, I have a stand alone GladeVCP example here: http://www.wallacecompany.com/machine_shop/LinuxCNC/gvcpDRO/
[16:04:34] <skunkworks> kwallace: thanks! that is what I am looking for.
[16:04:50] <kwallace> Cool.
[16:08:28] <cradek> sherline hasn't updated their install since 2011?
[16:28:56] <skunkworks> ouch
[16:43:38] <PCW> ~1 week at 4 KHz hm2_eth after I turned off _all_ fan controls (motherboard had 2 case fan controls in addition to CPU fan)
[18:05:25] <seb_kuzminsky> i bet a lot of these magic bios settings for latency would just disappear with coreboot
[18:22:01] <PCW> Yeah I didn't even notice these as they were scrolled off the bottom of the setup screen
[21:17:56] <skunkworks> zlog:
[23:40:33] <zeeshan> using a userspace component for controlling a vfd over modbus
[23:40:38] <zeeshan> is it a bad idea since it's too slow?