#linuxcnc-devel | Logs for 2014-08-09

[08:06:22] <jepler> seb_kuzminsky: yes, I vaguely recall this...
[08:17:53] <jepler> seb_kuzminsky: I wonder if this from dmesg is relevant [7629351.374551] ldpreload_main[1711]: segfault at 18 ip 00007f1fcb5fcc09 sp 00007fffc73f9b10 error 4 in libstdc++.so.6.0.13[7f1fcb533000+f6000]
[08:18:54] <jepler> oh maybe that's just the configure test for libgl buggerupness
[08:19:30] <jepler> ./ldpreload_main >/dev/null 2>&1
[08:19:32] <jepler> nevermind
[08:41:07] <jepler> seb_kuzminsky: to be honest I don't even know what that test is testing
[08:41:24] <jepler> "bug 357"
[08:42:28] <jepler> .. a crash
[08:42:34] <jepler> which could have been mah's fix or could have been my fix
[08:44:07] <jepler> seb_kuzminsky: from the buildbot log, it sure does look a lot like the test proceeded as intended but the timeout was too short
[10:36:57] <seb_kuzminsky> jepler: i think that's what it is, i extended the timeout and will keep an eye on it
[10:44:29] <KGB-linuxcnc> 03Sebastian Kuzminsky 052.6 8f3db8e 06linuxcnc 10VERSION 10debian/changelog update changelog & VERSION for 2.6.2 * 14http://git.linuxcnc.org/?p=linuxcnc.git;a=commitdiff;h=8f3db8e
[10:44:29] <KGB-linuxcnc> 03Sebastian Kuzminsky 05signed tags af36c2c 06linuxcnc 03v2.6.2 LinuxCNC v2.6.2 (tagged commit: 8f3db8e) * 14http://git.linuxcnc.org/?p=linuxcnc.git;a=commitdiff;h=af36c2c
[13:05:56] <jepler> [ 0.000000] NR_IRQS:549
[13:34:30] <jepler> pcw_home: with TXB0104 level translator, I've looped MOSI -> MISO and tested for reception at various rates. Vcca=1.8 Vccb=5.0. At 50MHz, messages are reliably echoed; by 75MHz, they aren't.
[13:34:58] <jepler> e.g., at 60MHz
[13:34:58] <jepler> 60
[13:34:58] <jepler> > 55aa f00f
[13:34:58] <jepler> < 55aa f00f
[13:35:12] <jepler> but by 75MHz
[13:35:12] <jepler> > 55aa f00f
[13:35:12] <jepler> < 2ad5 f807
[13:36:10] <jepler> (loop is on 5v side, exynos spi module is driving 1.8v side)
[13:38:53] <pcw_home> So thats probably mostly the delay contributed by the translator (did you try pokeing at the sample delay settings?)
[13:39:10] <jepler> no. I read the kernel enough that I believe it's initialized to 0
[13:41:40] <pcw_home> well if it translates it should work at _some_ frequency, tweaks or not
[13:42:09] <jepler> pcw_home: the toplevel that is needed for spi communicaton with hostmot2 is called what?
[13:42:31] <pcw_home> TopGCSPIHostMot2
[13:42:45] <jepler> OK
[13:44:13] <pcw_home> (GC=GlobalClock)
[13:44:14] <pcw_home> I have a AC version but not done yet (SPI clock is just another data input sampled at 200 MHz clockhigh)
[14:01:16] <pcw_home> There will be some issues making the TopGCSPIHostmot2 work with a 7I43 (since it was really only written for the 7I90 = SP6)
[14:01:17] <pcw_home> at the minimum the clocks (clockhigh,clocklow, clockmed) need to be lowered for the 7I43
[14:02:18] <pcw_home> (maybe, check if it meets timing)
[14:09:15] <jepler> still doing battle with the hostmot2-firmwares build system, nowhere close to checking timings :-/
[14:12:19] <pcw_home> I would cheat and use a project file :-)
[14:13:07] <pcw_home> need to do battle with some weeds
[14:13:08] <pcw_home> biab
[14:42:44] <jepler> > WARNING:Par:468 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in
[14:42:47] <jepler> your design.
[14:43:41] <jepler> the failing constraint is said to be TS_clkfx0 = PERIOD TIMEGRP "clkfx0" TS_CLK / 4 HIGH 50%
[15:09:24] <jepler> micges or pcw: I set my 7i43 with W4 down and W5 up, which should give me "USB Config". but mesaflash just hangs after writing octal 0377 to /dev/ttyUSB1
[15:09:40] <jepler> PWR: lit DONE: lit INIT: dark
[15:09:50] <jepler> what should I do next to troubleshoot?
[15:11:30] <CaptHindsight> is the installer broken on wheezy net ISO? Just tried it and after login the taskbar disappears and all that left is the desktop background
[15:14:09] <jepler> CaptHindsight: choosing an "install" option from the bootloader screen?
[15:18:24] <CaptHindsight> heh, I get the "Oh No" screen after a few minutes, can recover
[15:18:33] <CaptHindsight> can/can't
[15:19:30] <CaptHindsight> jepler: this is after the net install (1+ hour of downloads and installing of packages)
[15:20:36] <jepler> oh you're not talking about linuxcnc.org's binary.hybrid.iso, but about a debian.org iso?
[15:20:42] <jepler> I would be surprised if it were that broken
[15:21:38] <CaptHindsight> yeah, debian net ISO from debian.org, wanted to try it before adding Linuxcnc
[15:22:30] <jepler> OK, after power-cycling the card, mesaflash does detect it
[15:22:30] <jepler> $ ./mesaflash --device 7i43 --usb --addr /dev/ttyUSB1
[15:22:30] <jepler> USB device 7I43 at /dev/ttyUSB1
[15:23:29] <jepler> ERROR: Board 7I43 doesn't support FPGA resetting.
[15:33:44] <pcw_home> umm, you probably have to load a usb compatible config first
[15:34:45] <pcw_home> kind of a bootstrap operation...
[15:35:58] <jepler> pcw_home: hmm
[15:35:58] <jepler> [ 2164.352558] spidev spi1.0: I/O Error: rx-0 tx-1 res:rx-p tx-f len-4
[15:36:02] <jepler> uh oh, I made spi grumpy
[15:38:38] <jepler> pcw_home: after commenting out the reset in mesaflash, I can use --program with my bitfile
[15:38:46] <jepler> .. the DONE and INIT lights both go out, though mesaflash hangs
[15:39:38] <jepler> but in any case the firmware's not right. spi reads back gibberish
[15:40:03] <jepler> > 040ca860 00000000 00000000 00000000 00000000 00000000 00000000
[15:40:03] <jepler> < xxxxxxxx ff7ba86f fdfffffd ffffedff ffffffff fffffdff fffffffe
[15:44:29] <jepler> oh well, out of time for today
[15:45:25] <pcw_home> yeah its not likely to be right the first time
[15:50:06] <pcw_home> also maybe clock polarity and clock phasing (CPOL and CPHA)
[15:56:36] <jepler> it's possible it's that simple, or that I messed up my wiring
[15:57:03] <jepler> more likely that I've failed to properly adapt the spi firmware, which puts me well out of my depth
[16:02:25] <pcw_home> The SPI interface echos 0xAAAAAAAA on commands so that should be a a good minimal test
[16:03:16] <pcw_home> heck if you really want to mess with this I should send you a 7I90
[16:04:08] <pcw_home> so you are not trying to debug too many things at once
[16:09:01] <jepler> once again, I wouldn't say "no"
[16:09:38] <jepler> but this is way out further in left field than "I want to work on finishing hm2-eth"
[16:10:30] <jepler> (oh by the way, I was using mesaflash on arm to do the above usb talking)
[16:13:48] <pcw_home> The USB is serial port emulation so should run on most anything
[16:16:37] <pcw_home> What XXXXXXXX reads may be a clue to whats going wrong
[16:17:29] <pcw_home> (it may also be that you are not meeting timing so all data is funky)
[16:26:27] <jepler> > 040ca860 00000000 00000000 00000000 00000000 00000000 00000000
[16:26:27] <jepler> < ffffffff ffffffff ffffffff ffffffff ffffffff ffffff7f dbfddfff
[16:26:32] <jepler> I think it's just not talking spi
[16:27:20] <jepler> really gone this time
[16:27:29] <pcw_home> bye
[16:27:37] <jepler> pcw_home: thanks for the suggestions .. I think tomorrow I'll go back to assembler macros
[16:27:57] <pcw_home> do you have a active low CS?
[16:29:55] <jepler> yes
[16:30:14] <jepler> and I tried several but by no means all pha/pol options
[16:30:53] <pcw_home> even then I would not expect 0xFFFFFFFF
[16:33:19] <jepler> NET "COM_SPICLK" LOC = "p127" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
[16:33:49] <jepler> what is COM_SPICLK vs SPICLK?
[16:33:55] <jepler> NET "SPICLK" LOC = "p70" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
[16:33:58] <jepler> the former is the one I added..
[16:34:39] <pcw_home> this is 7i43.ucf?
[16:34:43] <jepler> modified from
[16:35:46] <pcw_home> the one thats there is for the flash memory (so is an output)
[16:35:48] <pcw_home> your new won should be an input (so n o drive or slew options)
[16:36:00] <pcw_home> new one
[16:36:12] <jepler> same for CS and IN then I guess
[16:36:25] <pcw_home> yep
[16:36:30] <jepler> I guess I should have read the other ucf
[16:37:21] <jepler> NET "COM_SPICLK" LOC ="P55" | IOSTANDARD = LVTTL;
[16:37:21] <jepler> NET "COM_SPIIN" LOC ="P56" | IOSTANDARD = LVTTL;
[16:37:21] <jepler> NET "COM_SPIOUT" LOC ="P57" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = FAST ;
[16:37:24] <jepler> NET "COM_SPICS" LOC ="P58" | IOSTANDARD = LVTTL;
[16:38:03] <pcw_home> Are you sure your ucf file is associated with the top level file?
[16:38:41] <jepler> yes, because I had errors that I resolved by editing it
[16:38:57] <pcw_home> also the 7I43 needs the funny config options mentioned in the manual (assert done last)
[16:41:31] <jepler> hm actually I got that wrong
[16:41:41] <jepler> I thought the build system would carry it over, but it's predicated on the board being an "epp"
[16:42:20] <pcw_home> if thats not done the configuration will not finish
[16:42:47] <pcw_home> but your not supposed to be fussing with this anymore :-)
[16:43:53] <jepler> > 040ca860 00000000 00000000 00000000 00000000 00000000 00000000
[16:43:53] <jepler> < 55555554 00000000 00000000 00000000 00000000 00000000 00000000
[16:44:06] <jepler> well something is different
[16:44:23] <jepler> really, *really* going this time
[16:44:54] <pcw_home> ahh looks close, bbl
[21:49:24] <skunkworks_> woke up this morning to the fridge not working... purchased in 09
[22:00:19] <jepler> skunkworks_: yuck
[22:15:23] <skunkworks_> I hope that it was just a bad fuse... (curcuit board mounted 15amp) it failed on one of the ends.. didn't open in the middle..
[22:15:35] <skunkworks_> replaced it and it is still running
[22:16:16] <skunkworks_> looks like maybe it wasn't soldered very
[22:16:21] <Tom_itx> sounds like it may have been faulty
[22:16:29] <skunkworks_> time will tell
[22:17:13] <Tom_itx> anything spoil?
[22:18:02] <Tom_itx> that can cost more than the appliance...
[22:18:56] <skunkworks_> heh - no. it must have happened close to the morning.. thought the bulb went bad - pulled the bulb and thought -'hey - the filament looks good'
[22:20:02] <skunkworks_> so after finding the fuse that looked fine was wide open - jumped it until I could solder some pigtails on some replacement fuses..
[22:20:17] <skunkworks_> so far so good.
[22:36:31] <skunkworks_> http://electronicsam.com/images/KandT/testing/stirling/stirling.jpg