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[13:59:35] <PCW> Spent a number of hours playing around with homing to index and dont see any issues (at least with master)
[13:59:37] <PCW> Todd has something strange going on though in that the count clearing seems one cycle late compared to mine:
[13:59:38] <PCW> freeby.mesanet.com/home-index.png
[13:59:40] <PCW> (his FB and cmd positions are cleared on cycle late)
[13:59:55] <PCW> one cycle
[14:03:02] <cradek> well that would sure do it
[14:03:43] <cradek> seems like his servo thread must be ordered wrong?
[14:04:17] <PCW> It looks right but I probably missed something
[14:04:57] <PCW> http://www.linuxcnc.org/index.php/english/forum/10-advanced-configuration/27806-linear-scale-correction-homing-to-index
[14:04:59] <PCW> is the thread
[14:06:31] <cradek> dabit = todd?
[14:06:51] <PCW> No Dabit started the thread
[14:07:24] <PCW> DAbit has the dual feedback system
[14:07:53] <PCW> Todd just chimed in to mention he had home-to-index thumps
[14:08:10] <PCW> or has I should say
[14:08:10] <cradek> oh I looked at that dig4w zip already
[14:08:22] <cradek> I agree the threads are in the right order in that particular zip
[14:08:32] <PCW> yes seem to be
[14:09:01] <cradek> perhaps the zip doesn't correspond
[14:09:19] <PCW> thats a possibility
[14:11:36] <cradek> man I hate web forums
[14:11:54] <cradek> can't I click somewhere and get an unmangled copy of his halscope plots?
[14:12:30] <PCW> he must have use JPEG or something
[14:12:38] <cradek> they're pngs
[14:12:43] <cradek> but something mangled them horribly
[14:14:08] <cradek> I guess I can see enough in the first one to see the position step is late
[14:14:22] <PCW> Yeah maybe high compression
[14:14:40] <PCW> so the PID masking fails
[14:14:47] <cradek> don't axis.0.encoder-pos-fb and axis.0.index-enable both come directly from hm2? how could they be read at different times?
[14:15:42] <cradek> don't axis.0.motor-pos-fb and axis.0.index-enable both come directly from hm2? how could they be read at different times?
[14:17:26] <cradek> yes in Dig4w they both come directly from hm2_5i25.0.xxx
[14:17:41] <cradek> it must be a hm2 problem if they don't happen together
[14:17:51] <PCW> Yes they certainly should (all in the hm2 read)
[14:17:58] <cradek> did you test with a 5i25 with his same firmware?
[14:18:31] <cradek> I can't imagine how it can be wrong but it must be - seems like it can not be a thread ordering problem
[14:19:20] <PCW> I'm using a 5i24 because its more convenient (encoder firmware has been the same for many years)
[14:20:49] <PCW> I'm not sure the hardware can do this but a driver bug might
[14:21:51] <cradek> he says he gets it even in 2.5.4
[14:29:09] <cradek> I'm pretty useless looking for it in encoder.c
[14:30:25] <PCW> yeah its not simple
[14:33:28] <cradek> do you think his report of "always X and sometimes Y" is accurate, or do you think it's just the differences in initial positioning?
[14:34:12] <PCW> I suspect its just how big the step is (so initial position)
[14:34:48] <cradek> he could test that, if he understands the initial position issue
[14:35:06] <cradek> if it really is only some axes that would be very interesting
[14:35:36] <cradek> and weird
[14:37:00] <PCW> Yeah Let me try a 5i25/7I77 to narrow this down
[15:20:13] <PCW> hmm they all change at the same time for me with 5i25/7i77
[15:20:23] <PCW> (and 2.5.0)
[15:22:17] <cradek> what could he possibly be doing differently
[15:25:18] <PCW> fairly mysterious
[15:26:02] <PCW> let me update to 2.5.4 and try that
[15:26:36] <PCW> (the live CD seems to be 2.5.0)
[15:47:29] <PCW> ok 5i25/7i77 ok with linuxcnc 2.5.0, 2.5.4, 2.7-pre0
[15:47:31] <PCW> OK meaning index enable falling edge happens at the same time as counter clear
[15:49:04] <cradek> so the plot thickens
[15:49:22] <PCW> the plot sickens
[15:50:10] <cradek> he's in ohio - too far for either of us
[15:51:40] <cradek> you could ask him to plot the hm2_ encoder pins directly. it would be impossible for any hal config problems to affect that result, even if he's misreported everything and sent us unrelated hal files
[15:52:46] <cradek> I think
[15:59:09] <PCW> Yeah that sounds like a good next test
[16:19:48] <kwallace1> Has anyone done any work on getting G76 to do tapered threads? I could add another flag to the C code in interp_convert, or I could start fresh with a remap in Python or O. The Fanuc code is different that LCNC code. Anything else I should consider?