#garfield Logs

Apr 11 2024

02:01 PM rob: Test
02:13 PM rob is now known as Guest9344
02:13 PM Guest9344 is now known as OK9UWU
02:13 PM OK9UWU: I've had a moment of insanity recently and decided to get into FPGA development.... Incredible for how cheap you can get extremelly capable boards... https://vi.aliexpress.com/item/1005005588402319.html
02:13 PM OK9UWU: extremelly capable for their price*
03:31 PM aandrew: oh yeah those LED panel driver boards are cheap as dirt these days
03:43 PM OK9UWU: got a simple UART TX to work https://ibb.co/FDsgFLZ , thats about it for tonight
03:43 PM OK9UWU: but honestly, as much as i heard that verilog is harder to learn than c, it seems quite the opposite to me :D
03:53 PM aandrew: I very much prefer VHDL to Verilog; I find Verilog and SystemVerilog too close to C for me and I end up writing more for software than hardware description
06:15 PM rue_mohr: I'm back
06:16 PM rue_mohr: which fpga is that?
06:17 PM rue_mohr: I think verilog is great
09:32 PM aandrew: it's a lattice ECP5 I think
09:32 PM aandrew: lattice for sure
09:32 PM rue_mohr: hmm, I'm not set up for those
09:32 PM rue_mohr: is it hard on linux?
09:32 PM aandrew: https://www.latticesemi.com/Products/FPGAandCPLD/ECP5 IIRC
09:33 PM aandrew: no, they have free but time locked (1yr I think) licenses
09:33 PM aandrew: however I also believe that Yosys can build bitstreams for them, check to be sure
09:34 PM rue_mohr: ah