#garfield Logs

Feb 08 2024

06:07 AM polprog: fuck xilinx for their shitty tools
07:51 AM rue_mohr: but their free tools
07:51 AM rue_mohr: can we trim it down to just a few hundred megs?
07:51 AM rue_mohr: they cant use that whole thing
09:19 AM aandrew: lol right
09:20 AM aandrew: all vendor tools suck. efinix is at least modern suck, followed by probably lattice or intel, then amd.
09:20 AM aandrew: older devices (and current lattice devices) can at least use the open source toolchains but sadly no vhdl there without a translation layer
10:44 AM polprog: spent entire day today bringing up linux on a ultrascale+ fpga
10:45 AM polprog: bloody thing
10:45 AM polprog: been trying to find out why it hangs on FPGA init
10:45 AM polprog: turned out that i missed a small warning by the boot image tool that embedding bitstreams is disabled if FPGA manager is enabled
10:46 AM polprog: (FPGA manager is something that lets you reprogram the FPGA fabric on the fly)
10:46 AM polprog: but there is a problem, if the kernel hangs because it expects a programmed FPGA peripheral as stated in the device tree, then it cant boot up to load the FPGA
10:46 AM polprog: took me 2 hours to notice that warning
10:47 AM polprog: bloody thing booted right up when i disabled the FPGA manager and included the bitstream in the boot file
11:08 AM aandrew: I got an A7-100T dev board, was going to get an ultrascale+ but they're using a7 here
11:16 AM aandrew: I've got quite a few fpga dev boards, smack my hands for looking at us+ boards
11:21 AM polprog: if you buy one then it's enough of a punishment
11:28 AM aandrew: hahaha
03:26 PM polprog: https://www.youtube.com/watch?v=dd16_Y9xfpw
03:26 PM polprog: extremely cursed
03:56 PM polprog: rue_mohr: https://www.youtube.com/watch?v=YA1Z_J-R-a8
03:56 PM polprog: encoders!
04:29 PM Tom_L: pays to read the fine print
06:20 PM rue_mohr: yike
10:40 PM rue_mohr: Hmm, hows that print going... ARG I DIDN'T START IT YET!!!