#garfield Logs

Oct 19 2023

02:35 AM polprog: rue_mohr: ive got a pythin "notebook" that runs it
02:48 AM polprog: ill make it into a regular script but that one uses some python numpy magic for multiplying the matrices and so on
02:48 AM polprog: i need.. a week off.. so i can finish all the projects
02:57 AM polprog: rue_mohr: the FPGA is rom configurable but the circuits that are made in it are not
02:59 AM polprog: So once the FPGA is ready you need to wait for some external signal before you go on and configure the circuits that you defined in the fpga
02:59 AM polprog: re: neural network
03:00 AM polprog: that algorhitm is the training, it gives you the weigths for the network
03:00 AM polprog: once you find them, you can just load them into an untrained network and it will work immediately
03:00 AM polprog: but the problem is how to find the weights
03:01 AM polprog: that linear regression problem is a bad example because you can solve it with one equation in one "iteration", its solved, you can do that in excel even (LINEST() ) function
03:02 AM polprog: but if you are fitting a different function, like, you want to fit exp(x) or something more complicated then you have to do it iteratively anyway
03:03 AM polprog: and back to fpgas, its a common thing now to implement the parts with premade IP cores
03:03 AM polprog: so you have a verilog code in the FPGA that behaves like a microcontroller peripheral
03:04 AM polprog: and in a similar way like you initialize the periph in microcontroller on boot (set baudrate for example) you have to initialzie that one in FPGA too
03:04 AM polprog: because its the same
03:04 AM polprog: in our case we use the AMBA AXI bus
03:04 AM polprog: becaus the peripherals we use are AXI peripherals
03:05 AM polprog: We could put a software core like ARM or RiscV there and it would work the same, but we dont need a full blown CPU inside there
03:05 AM polprog: so there is this tiny core available, all it can do is some simple conditionals and writing registers in the AXI peripherals
03:15 AM polprog: like, you can always write your own peripheral for uart or spi or some other random simple protocol
03:15 AM polprog: you can even make it use AXI because AXI is a simple bus
03:15 AM polprog: but once you need stuff like a DDR3 controller or PCI device/master.. things get hard
03:15 AM polprog: and you have to use a ready made IP core
07:33 AM rue_mohr: huh
08:23 AM rue_mohr: http://blog.tynemouthsoftware.co.uk/2023/10/how-the-zx80-generates-video.html
08:23 AM rue_mohr: http://blog.tynemouthsoftware.co.uk/2023/10/how-the-zx81-generates-video.html
08:32 AM polprog: off to home
08:38 AM rue_mohr: ?
01:43 PM polprog: im working now
01:43 PM polprog: pulling my hair to get PCI express runnin on a module that will go into a satellite (hopefully)
01:52 PM polprog: i mean "now"
01:53 PM polprog: not right now but i have a job as embedded software eng for 2 months now
06:33 PM rue_mohr: :)
10:07 PM rue_shop3: state machines
10:08 PM rue_shop3: oh, so the inflated shed failed
10:08 PM rue_shop3: when the power co shutdown the power for a day, it was raining hard,
10:08 PM rue_shop3: the rain sagged in the plastic over the airlock and tore one of the taped edges
10:09 PM rue_shop3: I'm trying to refind my roots
10:09 PM rue_shop3: foundation
10:09 PM rue_shop3: as i'v been kinda lost over the last month or more
11:15 PM aandrew: polprog: I've done some PCIe bringup, ping me if you want to bounce anything off of me
11:28 PM rue_shop2: Rue, design me a digital monostable