#garfield Logs

Sep 14 2023

08:24 AM rue_mohr: The T nuts arrived!
08:41 AM Tom_L: cool
08:41 AM Tom_L: yard done.. shower in a bit
01:49 PM aandrew: woo, made it out to colorado. tomorrow alburquerque, the day after phoenix and then lake forest
03:30 PM Tom_L: you really get around
04:30 PM aandrew: well the wheels on the car do
04:30 PM aandrew: can't believe how well it's been performing. 50mpg even fully loaded down
04:31 PM aandrew: 80-85mph the entire way
07:01 PM rue_mohr: root@blackie3:/opt/Xilinx/14.7/ISE_DS/ISE
07:04 PM Tom_L: ?
07:05 PM rue_mohr: copying a directory
07:06 PM rue_mohr: turns out the 9536 didn't work cause I was running it on 5V instead of 3.3
07:06 PM Tom_L: burn it up?
07:06 PM Tom_L: should be 5v tolerant
07:07 PM rue_mohr: no, its ok, but wont program at 5
08:19 PM rue_mohr: I'm having fun with the verilog ,cause its not *quite* like C
08:20 PM aandrew: that's why I don't like Verilog
08:20 PM aandrew: it's too close to C and I find myself trying to "write software" instead of "describing hardware"
08:22 PM rue_mohr: C but with a pascal overtone
08:22 PM aandrew: For some reason I can't quite put my finger on I rather LIKE VHDL's pendantic nature in a way I'd absolutely hate if C were the same way
08:23 PM rue_mohr: << and >> wont work, ok
08:25 PM rue_mohr: out <= {out[6],out[5],out[4],out[3],out[2],out[1],out[0],0};
08:26 PM aandrew: out <= out[6 downto 1] & '0'; :-)
08:27 PM rue_mohr: !! :]
08:27 PM aandrew: or better, out <= out[out'high - 1 downto out'low] & '0' if you want to make it more generic
08:27 PM aandrew: that's VHDL though not verilog
08:28 PM rue_mohr: out <= out[6 downto 0] & '0'; ?
08:29 PM rue_mohr: ,0
08:29 PM rue_mohr: out <= out[6 downto 0] , 0; ?
08:29 PM rue_mohr: 6 downto 0 should be 7 bits
08:31 PM rue_mohr: Due to other FF/Latch trimming, FF/Latch <out_7> (without init value) has a constant value of 0 in block <ring8>.
08:35 PM rue_mohr: wow, this is kicking my ass
08:35 PM rue_mohr: it keeps removing all the stuff for my ring counter
08:42 PM rue_mohr: it WONT do it
08:50 PM rue_mohr: if (out == 8'h00)
09:01 PM rue_mohr: it will not do it
09:01 PM rue_mohr: I'm resorting to simple tets
09:01 PM rue_mohr: tests