#garfield Logs

Apr 22 2022

01:28 AM rue_mohr: Critical Warning (332012): Synopsys Design Constraints File file not found: 'main.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
01:37 AM rue_mohr: ok
01:37 AM rue_mohr: oh thats funny
01:37 AM rue_mohr: it just chose pins
01:37 AM rue_mohr: U8_54 : L1 : output : 3.3-V LVTTL : : 1 : N
01:37 AM rue_mohr: U8_59 : L2 : output : 3.3-V LVTTL : : 1 : N
01:37 AM rue_mohr: U8_43 : L3 : output : 3.3-V LVTTL : : 1 : N
01:41 AM rue_mohr: Critical Warning (332148): Timing requirements not met
01:59 AM rue_mohr: Error (169059): I/O standard assignment 3.0-V LVCMOS to pin U8_41 is not supported by device File: /files/programming/fpga/altera/test1/main.v Line: 2
02:09 AM rue_mohr: ok got it to generate a svf file
02:30 AM rue_mohr: polprog, did you know the cyclone II has DSP IP cores?
02:34 AM rue_mohr: oh the cyclone II has a built in 10Mhz osc
02:44 AM rue_mohr: awe
02:44 AM rue_mohr: cant use it once its running tho
02:53 AM polprog: Oh neat
04:55 AM Tom_L: i think sometimes some pins have to be in the same block
08:32 AM aandrew: rue_mohr> if I say to a chip like that "toggle the LED pin" I dont expect it to just say "yup, ok!"
08:32 AM aandrew: heh yes that's exactly what it does. Anything not explicitly assigned will be automatically put on a pin
08:33 AM aandrew: rue_mohr> I think altera is using TCL for just about everything
08:33 AM aandrew: TCL is used with all vendors to my knowledge
08:33 AM aandrew: rue_mohr> I also need to work out the order to call the compile tools
08:33 AM aandrew: I have to figure that out every time I step away from it for a while
08:33 AM aandrew: fortunately the GUI logfiles are on by default and they give the exact command lines used
08:36 AM aandrew: rue_mohr> Critical Warning (332012): Synopsys Design Constraints File file not found: 'main.sdc'
08:37 AM aandrew: timing closure sucks but for 99% of simple stuff it's basically three lines:
08:37 AM aandrew: create_clock -period 8 -name CLOCK_SIGNAL_NAME [get_ports CLOCK_SIGNAL_NAME]
08:37 AM aandrew: derive_pll_clocks
08:38 AM aandrew: derive_clock_uncertainty
08:38 AM aandrew: that takes care of most of it
08:38 AM aandrew: feed a clock into a pin, assign that pin to the clock net in your design and make your .sdc file those 3 lines
08:39 AM aandrew: most times that clock will feed into a PLL and you'll have whatever clocks you want out of the PLL for your logic. the derive_pll_clocks and derive_clock_uncertainty is automatic in that case because the tools know what the PLLs are doing
08:40 AM aandrew: it gets hairy when you are working with source-synchronous interfaces or interfaces where the timing is so tight that you have to tell the FPGA the trace lengths so it can skew the signals to line up with the clocks at the target
08:40 AM aandrew: I don't want to talk about that, every time I think I understand it I end up wrong. Spent a LOT of time working with Altera clock specialists and I'm still frustratingly newb at it
08:41 AM aandrew: https://www.intel.com/content/dam/altera-www/global/en_US/uploads/3/3f/TimeQuest_User_Guide.pdf is the bible, I worked with Ryan trying to understand it and *HE* seems to think I understood it based on our communications, but I sure as hell feel like I dont
08:41 AM aandrew: rue_mohr> Critical Warning (332148): Timing requirements not met
08:42 AM aandrew: run it anyway - timing isn't met because it doesn't know what timing shoudl be but you're doing something slow enough and with no external clocking requirements so it'll be fine
08:51 AM rue_bed: :) cool!
09:22 AM rue_mohr: Tom_L, so far the docs dont tell me what pins are part of which blocks
09:22 AM rue_mohr: in the datasheet I expected a 'ballout'
09:23 AM rue_mohr: all I have to go by is the .pin file created by the tools
09:25 AM rue_mohr: aandrew, on xilinx, the file to assign pins isn't tcl
09:25 AM rue_mohr: the altera one looks like it is
09:29 AM rue_mohr: I wonder what reads a .sdc file...
10:01 AM aandrew: rue_mohr: that's *definitely* in the datasheet
10:01 AM aandrew: and it's also *definitely* in the GUI pin planner
10:01 AM aandrew: rue_mohr: the fitter reads the SDC file if I remember correctly
02:15 PM Tom_L: rue_mohr, the graphic tool would show you i think
03:04 PM Tom_L: found a couple 1/16 ball nose today
05:22 PM rue_mohr: :)
05:22 PM rue_mohr: aandrew, maybe I had the wrong datasheet
05:22 PM rue_mohr: they showed the mechanical for the bga, but not the ballout
05:26 PM Tom_L: rudolph with the led nose
05:27 PM rue_mohr: :)
05:28 PM rue_mohr: if it works maybe I can find some clear stuff :)
05:37 PM rue_mohr: so I need to see if I can load that svf file to an fpga
05:41 PM Tom_L: is that their form of bit file?
05:42 PM rue_mohr: yes, I suppose
05:42 PM rue_mohr: or just another form
06:29 PM rue_mohr: weekend goals
06:29 PM rue_mohr: todo: find todo list
06:29 PM rue_mohr: todo: strip down a printer or two
06:29 PM rue_mohr: todo: sprayer billing
06:29 PM rue_mohr: todo: test altera programming via openocd
08:58 PM aandrew: rue_mohr: there are about eleventeen datasheets for a given FPGA, the break it down because the single file would be pretty big (and things like I/O standards/etc are the same for all devices in the same family)
10:41 PM rue_shop3: I wonder what the keyword is for the ballout datasheet