#garfield Logs

Aug 16 2021

11:21 AM aandrew: hah
11:29 AM aandrew: I just realized (rather a guy running the test for me) that the op-amp I'm using is UNcompensated
11:29 AM aandrew: it's oscillating at 11MHz
11:29 AM aandrew: ~1.5v p-p on top of a 1.25V DC input signal
11:29 AM aandrew: I never was good at this pole/null stuff
02:53 PM rue_mohr: that throws them off
02:53 PM rue_mohr: what blew me away was learning that some op-amps aren't stable at unity
02:53 PM rue_mohr: aka buffer
02:53 PM rue_mohr: is the setup simple? I'm looking for a op-amp circuit to try to stabalize
02:54 PM rue_mohr: apparently adding a resistor to the output helps
03:06 PM Tom_L: how do i invert a reg?
04:42 PM polprog: in verilog?
04:45 PM Tom_L: done already
04:45 PM Tom_L: but yes
04:45 PM polprog: :)
04:51 PM Tom_L: rue coaxed me into draging out my spartin board
04:54 PM polprog: good ;D you can run my 8051 setup then
06:26 PM Tom_L: polprog, you prefer verilog over vhdl?
08:07 PM rue_shop3: ooo fpga 8051?