#garfield Logs

Jul 23 2021

12:28 AM polprog: morning
12:35 AM polprog: i have to rewrite a part of my verilog
12:35 AM polprog: i cant get round to it :/
12:40 AM rue_mohr: if you have access to a 3d printer, round-tuits can be obtained
12:41 AM rue_mohr: https://www.thingiverse.com/thing:6016
12:55 AM rue_mohr: well thanks tom, I might throw togethor a small fpga board
12:55 AM rue_mohr: I need to finish by BGA cpld baord!
08:58 AM rue_mohr: morning
09:25 AM polprog: I still have these chinese FPGA led controller boards, i wonder what could be done with them
09:28 AM rue_mohr: what fpga?
09:33 AM polprog: https://github.com/q3k/chubby75
09:33 AM polprog: Lattice ECP5
09:33 AM rue_mohr: lattive
09:33 AM rue_mohr: hmm
09:33 AM rue_mohr: yosys?
09:34 AM polprog: sounds like it
09:34 AM polprog: theres a version with spartan 6 (3rd picture) but i havent seen it online
09:36 AM polprog: https://github.com/q3k/chubby75/blob/master/5a-75b/README.md
09:36 AM polprog: this one is mine
09:37 AM rue_mohr: I dont think I have any lattice chips,
09:38 AM rue_mohr: I do have some alteara
09:39 AM rue_mohr: I'v never seen a 4 pin jtag before!
09:39 AM rue_mohr: whats with that
09:40 AM polprog: tdi do tms tck
09:40 AM polprog: tdo*
09:40 AM rue_mohr: well its a lot of output lines anyhow
09:40 AM polprog: trst is not necesary, clocking several high states on tms is like a reset
09:40 AM polprog: o something
09:40 AM polprog: or*
09:44 AM rue_mohr: no but usually power is included
09:45 AM rue_mohr: I'm off next week, mostly
09:47 AM polprog: wdym?
09:52 AM rue_shop3: vaccation for a week
09:52 AM polprog: oh nice
11:12 AM polprog: https://twitter.com/polprogpl/status/1418601238363611140?s=19
01:58 PM polprog: rue_mohr: i recall you did some s&h circuit but im going to the forest for the weekend
01:58 PM polprog: so i can play with it on monday
01:58 PM polprog: well deserved holidays :v
06:43 PM Tom_L: rue_mohr made me get the fpga board out and dust it off, look at it and put it back in the drawer
07:04 PM rue_mohr: hah
07:31 PM rue_mohr: ok I'm gonna rest and work on the i2c more
10:01 PM rue_bed: TEA ME UP!
11:18 PM rue_shop2: module clockDown ( Clk, Counter, MaxCount );
11:18 PM rue_shop2: input Clk;
11:18 PM rue_shop2: reg [$clog2(MaxCount+1) : 0] Counter;
11:18 PM rue_shop2:
11:18 PM rue_shop2: always @(negedge Clk)
11:18 PM rue_shop2: if (Counter == 0) Counter = MaxCount;
11:18 PM rue_shop2: else Counter = Counter - 1;
11:18 PM rue_shop2: endmodule
11:18 PM rue_shop2: no generic countdown module today
11:26 PM rue_mohr: i2cRead C1 (bitSelect, 16'b0, D, C);
11:26 PM rue_mohr: assign P[0] = ( D == 0 ) ? 0 : z;
11:26 PM rue_mohr: assign P[1] = ( C == 0 ) ? 0 : z;
11:26 PM rue_mohr: ?
11:31 PM Tom_L: oooo kibbles n bits n bytes
11:31 PM rue_shop2: so, the next step is to make it open collector and see if the ROM answers
11:31 PM rue_shop2: I think it will
11:31 PM rue_shop2: so I'v set the reply bits to FF
11:32 PM rue_shop2: I should set up the fpga for this while I'm playing, I'm gonna wear out the cpld I dead bugged
11:32 PM Tom_L: mmm, past my bedtime
11:33 PM Tom_L: you got more ehh?
11:33 PM rue_shop2: :/ not set up dead bug bga
11:33 PM Tom_L: but bga is easy!
11:34 PM Tom_L: see you at 4... gnite
11:49 PM rue_shop3: yes!
11:49 PM rue_shop3: the chip replied! 0xA1
11:58 PM rue_shop2: next I need to substitute in the address bits