#garfield Logs

Jul 21 2021

09:15 AM rue_mohr: wire [0:98] data = {20'b10110011000000000000, 16'b1111000011000000, 2'b00, 16'b1100001100110000, 24'b000010110011000000001100, 16'b1111111111111111, 5'b00001 };
09:22 AM rue_mohr:
09:22 AM rue_mohr: assign d = data[bitSelect];
09:22 AM rue_mohr: tho, I'm not sure I have the endian-ness right
12:49 PM Tom_L: that's some big numbers
07:24 PM Tom_L: rue_mohr, what's this coupler you speak of?
07:27 PM rue_mohr: its a coupler for a blander
07:27 PM rue_mohr: It turns out one of his major dimentions isn't right
07:28 PM Tom_L: how's that tiny one holding up?
07:29 PM Tom_L: on the router or whatever it was
07:29 PM rue_mohr: the one I made?
07:29 PM Tom_L: that plastic thing i sent
07:29 PM rue_mohr: oh
07:29 PM rue_mohr: right
07:29 PM Tom_L: been a while
07:29 PM rue_mohr: I'll ask him
07:30 PM rue_mohr: I forgot about that
07:30 PM Tom_L: tell him the warranty expired yesterday
07:30 PM rue_mohr: I suspect its fine as he didn't say anyting
07:30 PM Tom_L: http://tom-itx.no-ip.biz:81/~webpage/rue/coupler/Coupler3.jpg
07:30 PM Tom_L: i nearly forgot about those
07:37 PM rue_mohr: yep
07:37 PM rue_mohr: I forget, did we have to adjust to get it to work
07:37 PM rue_mohr: ?
08:04 PM rue_mohr: huh, I cant get the bits to reverse on the cpld
08:04 PM rue_mohr: wire [0:98] data = {20'b10110011000000000000, 16'b1111000011000000, 2'b00, 16'b1100001100110000, 24'b000010110011000000001100, 16'b1111111111111111, 5'b00001 };
08:04 PM rue_mohr: so I need to reverse this myself
08:05 PM aandrew: rue_mohr: oh that's verilog, I don't know verilog very well but couldn't you use the equivalent to a generate statement
08:08 PM aandrew: something like the verilog equiv of for i in wire'range wire(i) <= in(in'high - i); end generate ?
08:08 PM aandrew: you may even be able to say wire[98:0]
08:08 PM aandrew: I know that works in vhdl
08:10 PM Tom_L: rue_mohr, i don't think so, i think it fit
08:15 PM rue_mohr: I treid 98:0 and it barked at me
08:15 PM rue_mohr: not due to that but the contents I was trying to set it to
08:15 PM rue_mohr: I suppose, I should be able to make a wire map to reverse it
08:16 PM rue_mohr: technically i have all the lsb and msbs mixed up tho
08:17 PM rue_mohr: tho
08:17 PM rue_mohr: where do bits end up..
08:17 PM rue_mohr: if I say wire [7:0] foo = 8'b11110000 ;
08:18 PM rue_mohr: who ends up where tho
08:19 PM rue_mohr: and the problem is that if I have a little endian and a large endian value, I cant just assign them from the other
08:19 PM rue_mohr: well I can explicitly
08:19 PM rue_mohr: trying to avoid that
08:20 PM aandrew: it follows in order I thought
08:21 PM aandrew: so foo[7..4] = 1 and [3..0] = 0
08:21 PM rue_mohr: it barfs on mixed endians foo[0:7] = { bla[3:0], yak[3:0] } ; is not happy
08:21 PM rue_mohr: I'v not tried .. tho
08:22 PM rue_mohr: is that a vdhl specific thing?
08:22 PM aandrew: I'm not sure. I kind of say away from verilog because it triggers all my C programming neurons
08:22 PM rue_shop3: I think I should play with some lights
08:23 PM aandrew: I'm stuck in a bathroom on set
08:23 PM aandrew: literally
08:23 PM rue_shop2: I find the "coding hardware" is bending my mind in awesome ways
08:23 PM rue_shop2: hah
08:23 PM aandrew: I'm literally sitting on a little folding camping stool (not chair) that I bought because this was the only place I could have a counter while waiting for my son to do his thing
08:23 PM aandrew: it looks a little silly but it's not bad
08:23 PM aandrew: rue_mohr: yes - learning VHDL has permanently altered how I approach software in good ways
08:24 PM Tom_L: bending or warping?
08:24 PM aandrew: I'm more ... explicit
08:24 PM rue_shop2: well, I'v had a few times that thinking how I would implment something in hardware has changed my software approach
08:24 PM aandrew: yep
08:25 PM Tom_L: fpga/cpld are fun
08:25 PM rue_shop2: I have those really big bga fpgas that...
08:25 PM rue_shop2: I'm tempted
08:25 PM rue_shop2: now that the dead bug thing works
08:25 PM Tom_L: those need flash attached
08:26 PM Tom_L: or you reprogram each time
08:26 PM rue_shop2: sure, whatever
08:26 PM Tom_L: they will hold it until you turn them off
08:26 PM rue_shop2: just playing with them dynamically might be fun too
08:26 PM rue_shop2: yea
08:27 PM aandrew: I really like the ICE4x devices and MachXO2/3 from Lattice. Their tools aren't the greatest but the devices are decent performers
08:27 PM aandrew: and they have friendy(ier) packages
08:27 PM rue_shop2: can I do them on linux?
08:29 PM Tom_L: the tool chain was always the good thing about xilinx
08:29 PM Tom_L: one of those 68332 boards i have has a couple fpga on it
08:30 PM Tom_L: they may be lattice, i don't remember
08:30 PM rue_shop2: this dead bug cpld has been nice, descent amount of space
08:30 PM Tom_L: he put the jtag in one i know
08:30 PM rue_shop2: I'm still working on the pcb, I need to see what 3.3V linear regulators I have around
08:31 PM aandrew: rue_mohr: yes, both Diamond and IceCube work on Linux
08:31 PM aandrew: I've also successfully programmed them with an STM32 over SPI which was handy
08:32 PM Tom_L: those sound like rappers :)
08:33 PM aandrew: Tom_L: hahaha
08:33 PM aandrew: lattice's licensing *sucks* (it's free, but always timelocked, your license lasts only a year and you have eto renew it (get a new file))
08:34 PM Tom_L: i knew there was something weird about them
08:36 PM Tom_L: is intel still in the fpga business? altera
08:47 PM Tom_itx: https://grabcad.com/challenges/nasa-challenge-lunar-torch?mkt_tok=NTMzLUxBVi0wOTkAAAF-aV2gmCMWd0y5bmqJunMjBRemd6p3CL---Yl8vR4E24olx331TYGVmm1AdH8k93cQmz-KkasOIV2SOGIVQbiIQRIWGAnVAJDIrgJw_cXIecHTyas
08:50 PM rue_shop2: aha
08:51 PM rue_shop2: the old "nothing I do to this code changes the devices operation" via "wait, I'm flashing the device with the wrong project"
08:52 PM rue_shop2: but the dev tools work on linux too?
08:52 PM rue_shop2: hmm
08:53 PM rue_shop2: diamond and icecube
08:53 PM aandrew: rue_mohr: yes, I only use linux with FPGA work
08:53 PM rue_shop2: :) ah cool
08:53 PM aandrew: wish I could use OSX but that'll never happen
08:53 PM rue_shop2: and vdhl huh
08:53 PM aandrew: and the Linux ABI for OSX looked awesome, but was dropped
08:54 PM aandrew: yes I do VHDL but that's not a requirement
08:54 PM aandrew: just a personal preference
08:54 PM rue_shop2: I'll ahve to see if I have any alteara devices around
08:55 PM rue_shop2: S002A EP1810LC-35T
08:56 PM rue_shop2: mach110
08:56 PM rue_shop2: EPM7032
08:57 PM aandrew: I have a few of the perceptron design I did, those have a really nice STM32F756 and a 10M50 on them
08:57 PM rue_shop2: line 46 Indices in part-select of vector wire 'data' are reversed
08:57 PM aandrew: and i have a couple of the bare chips on my bench, I have to reball them though but they should be perfectly functional
08:58 PM rue_shop2: just dead bug 'em :)
08:58 PM aandrew: yeah I could in theory
08:58 PM aandrew: I wired them up nice too
08:58 PM aandrew: SPI/I2C/16-bit parallel, and the FPGA has a ... SDR? DDR? interface to a few megs of DRAM too
08:58 PM aandrew: but alas, -ENOTIME
08:59 PM aandrew: oh and gigabit ethernet, although it's got a goofy-ass connector because it interfaces with one of their PoE boards
08:59 PM rue_shop2: so, once the endian has been presented, it cannot be reversed
09:00 PM rue_shop2: huh, no reversi
09:01 PM rue_shop2: I should probably just reverse the bit order of the playback
09:01 PM rue_shop2: if it starts from the msb and works down
09:02 PM rue_shop2: its just symantic anyhow
10:05 PM rue_shop2: huh, has to be a register, not a wire
10:06 PM Tom_L: yeah
10:06 PM Tom_L: i recall something about that
10:11 PM aandrew: hm?
10:11 PM aandrew: you have to use reg?
10:11 PM aandrew: reg/wire is one of those things that seemed poorly defined in verilog
10:11 PM aandrew: one of the reasons I really like vhdl :-)
10:11 PM aandrew: delta cycles FTW
10:16 PM rue_shop2: ok, its not using latches for it tho
10:17 PM rue_shop2: trying to view the schematic for that simple thing gave it trouble tho
10:17 PM rue_shop2: "How did you do that" "I dont know"
10:17 PM rue_shop2: wire [7:0] data = 8'b11110000;
10:17 PM rue_shop2: reg [7:0] reversed;
10:17 PM rue_shop2:
10:17 PM rue_shop2: always @* begin
10:17 PM rue_shop2: for ( n=0 ; n < 8 ; n=n+1 )
10:17 PM rue_shop2: reversed[n] = data[7-n];
10:17 PM rue_shop2: end
10:17 PM rue_shop2:
10:17 PM rue_shop2: assign P[7:0] = reversed;
10:18 PM rue_shop2: a bit laborious tho
10:20 PM aandrew: rue_mohr: is there no generate in verilog?
10:21 PM aandrew: there is
10:21 PM aandrew: for (i=0; i<8; i++) begin
10:21 PM aandrew: P[n] = data[7-n];
10:21 PM aandrew: endgenerate
10:21 PM Tom_L: http://www.asic-world.com/verilog/veritut.html
10:21 PM aandrew: you also need to declare i as genvar (genvar i);)
10:21 PM aandrew: er
10:21 PM aandrew: genvar i;
10:28 PM rue_mohr: oh
10:32 PM rue_shop2: looks like I have to use i=i+1
10:38 PM rue_shop2: "generated begin-end blocks must be named"
10:40 PM aandrew: right, I posted pseudoverilog
10:40 PM aandrew: https://www.chipverify.com/verilog/verilog-generate-block
10:42 PM rue_shop2: I'm being highly amused how examples from the net dont work
10:43 PM aandrew: oh for sure
10:43 PM aandrew: bane of everyone having their own printing press, but a small price to pay
10:47 PM rue_shop2: so from what I understand, generate is supposed to act like a macro block and bang out the verilog as per the for loop unrolled
10:47 PM rue_shop2: but
10:49 PM rue_shop2: I'm also highly bothered by examples being pseudocode that dont actually do things on an electronic cpld/fpga
10:49 PM rue_shop2: things based on logic and printing messages
10:55 PM rue_shop2: it looks like generate isn't meant for this tho
10:55 PM rue_shop2: its meant for replicating modules
11:23 PM rue_shop2: starting to think I'm gonna wear out my cpld
11:38 PM aandrew: rue_mohr: exactly re: what generate does
11:38 PM aandrew: I use it to automate repetitive assignments
11:52 PM rue_mohr: it cant automate this one tho
11:52 PM rue_mohr: there is a restruiction