#garfield Logs
Jan 23 2021
#garfield Calendar
12:02 AM rue_mohr: XC6SLX16
12:08 AM rue_mohr: NET test_signal_p LOC = "P51" | IOSTANDARD = LVDS_33;
12:08 AM rue_mohr: NET test_signal_n LOC = "P50" | IOSTANDARD = LVDS_33;
12:08 AM rue_mohr: ok
03:47 AM rue_mohr: filters are crazy important
03:47 AM rue_mohr: not only building them, but understanding how they occur in nature
03:48 AM rue_mohr: PID is a type of filter
03:48 AM rue_mohr: it boosts high and low frequencies to idealize the natural system response
03:48 AM rue_mohr: (it does it in a really awefull way tho)
01:19 PM rue_mohr: so the idea then is to set up a comparator using a diff input, then see what the schmitt is like
02:08 PM rue_mohr: I totally remembered while I was in the shower
02:08 PM rue_mohr: the reason that I wanted to master RC was to make a better DAC,
02:09 PM rue_mohr: If you simulate the 1 bit ADC in code, you can generate the 1 bit stream and use an RC to regenerate it on the outside
02:10 PM Tom_L: you had an ah hah moment
02:14 PM polprog: haha
02:40 PM aandrew: yep filters are very important
02:40 PM aandrew: one of the understatements and most misunderstood things in signal processing
02:40 PM aandrew: aliasing and image rejection are real
03:07 PM polprog: rue_mohr: ive learnt how to make deb packages :)
03:07 PM polprog: https://polprog.net/rozne1/ircjunk/debs/
03:07 PM polprog: you can grab rclib from there
03:07 PM polprog: so now rclib can install via install(1) or a deb package
03:08 PM Tom_L: i posted one a while back on how to do that
03:10 PM Tom_L: https://jethornton.github.io/stdeb/console.html
03:10 PM Tom_L: creates a menu entry as well
03:13 PM polprog: python implementation
03:14 PM polprog: bookmarked
03:14 PM polprog: mine is all in makefike
03:14 PM polprog: makefile*
03:15 PM Tom_L: he's got one for a gui there too
03:15 PM polprog: yeah
03:15 PM Tom_L: i've done kernels to deb
03:16 PM rue_mohr: polprog, hah cool
03:31 PM polprog: wtf
03:31 PM polprog: git rebase -i HEAD~4
03:31 PM polprog: generates a todo, that is totally unordered and is 9 commits total
03:31 PM polprog: WTF
03:48 PM Tom_itx is now known as Tom_L
04:19 PM polprog: ok solved
04:22 PM Tom_L: https://www.amazon.com/gp/product/B085XPHY77/ref=ox_sc_saved_title_3?smid=AOP0CH6UTUPHT&psc=1
04:22 PM Tom_L: my rpi4 case but with a riser for the header
04:23 PM Tom_L: i wish i knew what those were called on digikey
06:04 PM rue_mohr: hmm
07:47 PM rue_mohr: polprog, the goal is to make a FPGA comparator
07:55 PM polprog: like an fpga analog comparator?
07:57 PM rue_shop3: yea, you use a differential input
07:57 PM rue_shop3: tho mine aren't easy to get at
07:58 PM rue_shop3: yea, this will take some work
07:58 PM rue_shop3: iirc whitequark set up a serial port on each pin, and transmitted the pin number
07:58 PM rue_shop3: all at once
08:01 PM rue_shop3: ok solder on some new pins...
08:08 PM rue_shop3: for my first trick I will start the IDE and make an led flash
08:10 PM rue_shop3: opt/Xilinx/14.7/ISE_DS/ISE/bin/lin/_pn: error while loading shared libraries: libSM.so.6: cannot open shared object file: No such file or directory
08:11 PM Tom_L: what you up to now?
08:11 PM rue_shop3: ^^ using a differential input as ana analog comparator
08:12 PM rue_shop3: frist I have to make it all work again
08:12 PM rue_shop3: its not just as easy and point and click
08:14 PM rue_shop3: I cant find my instructions on how to write to the chip
08:14 PM rue_shop3: ah its on paper
08:15 PM rue_shop3: but not any of the pages in my fpga box
08:16 PM rue_shop3: aha
08:16 PM rue_shop3: xc3sprog -c ft232h main.bit
08:17 PM rue_shop3: ok! I got an LED flashing!!!!
08:18 PM rue_shop3: so, I'll get the button -> led demo working, then modify it
08:35 PM rue_shop3: ok! I got the buttons operating the leds
08:37 PM Tom_L: fpga review time
08:38 PM rue_shop3: yea I'm trying to clean up the directory a bit too
08:38 PM rue_shop3: each project is 36M of files
08:43 PM rue_shop3: I'm on connector U7
08:44 PM rue_shop3: I'm on pins 17/18
08:44 PM rue_shop3: F15, F16
08:44 PM rue_shop3: bank 1
08:45 PM rue_shop3: 3.3V
08:55 PM rue_shop3: hmm
08:56 PM rue_shop3: if I configure one part of a pair to be lvds, will the other half just follow along?
08:57 PM Tom_L: pins?
08:57 PM Tom_L: i'm not sure
08:57 PM rue_shop3: F15 and F16
08:58 PM rue_shop3: NET test_signal_p LOC = "P51" | IOSTANDARD = LVDS_33;
08:58 PM rue_shop3: NET test_signal_n LOC = "P50" | IOSTANDARD = LVDS_33;
08:58 PM rue_shop3: The I/O component "diff_p" has an illegal IOSTANDARD value.
08:58 PM rue_shop3: The IOB component is configured to use single-ended signaling and can not use
08:58 PM rue_shop3: differential IOSTANDARD value LVDS_33. Two ways to rectify this issue are:
08:58 PM rue_shop3: 1) Change the IOSTANDARD value to a single-ended standard. 2) Correct the I/O
08:58 PM rue_shop3: connectivity by instantiating a differential I/O buffer.
08:58 PM rue_shop3: ^^ is what I was trying to paste
09:04 PM Tom_L: a bit rusty but do the pins fall on what i would call a boundary such that they can't be a differential pair?
09:04 PM rue_shop3: they are differential pins
09:04 PM rue_shop3: something just says their not
09:05 PM Tom_L: mmm
09:19 PM rue_shop3: wtf...
09:19 PM rue_shop3: U7 9,10
09:20 PM rue_shop3: B15,B16
09:20 PM rue_shop3: all bank 1
09:21 PM Tom_L: you said F15 F16 earlier
09:21 PM rue_shop3: yea, I'm gonna try other pins
09:21 PM rue_shop3: cause, WTF
09:22 PM rue_shop3: I think it does't want me to use diff on bank 1
09:22 PM rue_shop3: not sure why
09:23 PM rue_shop3: The I/O component "diff_p" has an illegal IOSTANDARD value.
09:23 PM rue_shop3: The IOB component is configured to use single-ended signaling and can not use
09:23 PM rue_shop3: differential IOSTANDARD value LVDS_33. Two ways to rectify this issue are:
09:23 PM rue_shop3: 1) Change the IOSTANDARD value to a single-ended standard. 2) Correct the I/O
09:23 PM rue_shop3: connectivity by instantiating a differential I/O buffer.
09:23 PM rue_shop3: whats IOB
09:24 PM Tom_L: https://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/Place-1018-clock-IOB-and-clock-component-placement-error-Spartan/td-p/81111
09:24 PM Tom_L: clock related?
09:26 PM Tom_L: https://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/Spartan-6-IOSTANDARD-error-for-differential-signal/td-p/823664
09:26 PM rue_shop3: maybe I need to rebuild the project?
09:26 PM Tom_L: look at that 2nd one
09:27 PM rue_shop3: IBUFDS
09:27 PM rue_shop3: example?
09:28 PM Tom_L: https://forums.xilinx.com/t5/Virtex-Family-FPGAs-Archived/How-to-use-IBUFDS-OBUFDS-differential-signals-buffers-for-Virtex/td-p/63576
09:29 PM rue_shop3: what!?
09:30 PM Tom_L: that's virtex...
09:30 PM rue_shop3: I just want to know if the differetial pair is 1 or 0
09:30 PM rue_shop3: maybe we can find a really simple example?
09:31 PM Tom_L: http://hunteng.co.uk/pdfs/tutor/FPGA_Digital_IOs.pdf
09:32 PM rue_shop3: does it say how to do it
09:33 PM rue_shop3: takes me 2 mins to open a pdf cause of god damn freaking software that wont do what you tell it to
09:33 PM Tom_L: https://stackoverflow.com/questions/57362230/is-it-possible-to-switch-between-single-ended-and-differential-io-on-the-fly
09:35 PM rue_shop3: the pdf didn't say how to do it tho
09:35 PM rue_shop3: its missing the pin information
09:35 PM Tom_L: i don't think i've done anything like that
09:36 PM rue_shop3: its hardware stuff
09:37 PM rue_shop3: it looks like there is something you need to specify in the ucf file
09:38 PM rue_shop3: DIFF_TERM = TRUE
09:39 PM rue_shop3: XILINX FPGA offers on-chip terminators by the name of "DIFF_TERM"
09:39 PM rue_shop3: ^^ nope
09:44 PM Tom_L: https://electronics.stackexchange.com/questions/248336/driving-a-differential-signal-from-fpga
09:44 PM rue_shop3: to fpga?
09:45 PM rue_shop3: so, do differential inputs HAVE to be clocked?
09:47 PM Tom_L: as a guess i would say so but it's a guess
09:47 PM rue_shop3: https://electronics.stackexchange.com/questions/93373/how-to-route-a-lvds-clock-from-fpga-input-to-output
09:49 PM rue_shop3: https://blog.csdn.net/u013273161/article/details/88532055
09:49 PM rue_shop3: ooh^^
09:49 PM rue_shop3: so them as single and constrain them after
09:49 PM rue_shop3: with a different name
09:51 PM rue_shop3: I need to know if
09:51 PM rue_shop3: F15 is positive or neg
09:52 PM Tom_L: they can't go either way?
09:52 PM rue_shop3: no
09:52 PM rue_shop3: Attribute value "LVDS33" is not an accepted value for
09:52 PM rue_shop3: attribute "IOSTANDARD" on "diff_p".
09:53 PM rue_shop3: ^^^ dont forget the underscore
09:57 PM rue_shop3: there is still a cloud of black voodoo
09:58 PM Tom_L: if you could catch pcw in a good mood in linuxcnc he could tell you how to do it
09:59 PM rue_shop3: I'll try a bit longer
09:59 PM Tom_L: he is mesa
09:59 PM rue_shop3: I just need _1_ complete example
09:59 PM Tom_L: and what should the example do?
10:00 PM rue_shop3: take a single diff input and operate a single ended led with it
10:00 PM rue_shop3: diff input -> single ended led output
10:01 PM Tom_L: my daughter board is all differential and he had me load one side with resistors
10:01 PM rue_shop3: I just want a basic test of a single differential input
10:02 PM Tom_L: https://forums.xilinx.com/t5/Other-FPGA-Architecture/Using-Spartan-6-differential-input-as-comparator-an-electrical/td-p/977109
10:05 PM Tom_L: https://www.eetimes.com/xilinx-spartan-6-fpga-user-guide-lite/
10:06 PM rue_shop3: only articles with code are usefull here
10:06 PM Tom_L: https://www.pantechsolutions.net/blog/adc-interface-with-xilinx-spartan-fpga/
10:07 PM rue_shop3: only articles with code
10:07 PM Tom_L: VHDL code for ADC
10:08 PM Tom_L: ur gettin kinda picky
10:08 PM rue_shop3: the target article should include the string IBUFDS, I think
10:08 PM rue_shop3: I dont need it for an adc
10:08 PM rue_shop3: I just want a differential input to a single ended output
10:09 PM rue_shop3: but it needs to be real differential mode, not done with a lookup table
10:09 PM rue_shop3: which is what I think some of these are doing
10:12 PM aandrew: ooh I know about this
10:12 PM aandrew: let me reread history
10:12 PM aandrew: done quite a bit of FPGA stuff
10:12 PM rue_shop3: we got nowhere, please tell
10:12 PM rue_shop3: goal is one diff pair to a single ended output
10:13 PM rue_shop3: IBUFDS isn't making sense
10:13 PM rue_shop3: they seem to not relate the signal names in it to the signals they are using
10:13 PM rue_shop3: or.. thats what I'm trying to udnerstand
10:14 PM Tom_L: https://www.eevblog.com/forum/microcontrollers/lvds-input-on-spartan6/
10:14 PM aandrew: you can use a diff input as a comparator but it's not really designed for that
10:15 PM rue_shop3: yea, I want to play, but I cant get any diff input to work
10:15 PM rue_shop3: aka it wont compile
10:15 PM Tom_L: take a look at that one
10:16 PM rue_shop3: so then what signal name do you use?
10:16 PM rue_shop3: they skipped that bit
10:16 PM rue_shop3: https://blog.csdn.net/u013273161/article/details/88532055
10:17 PM rue_shop3: ^^ in that code, they make their positive and neg inputs then relate them with the ibuff
10:17 PM rue_shop3: but then dont use them
10:17 PM rue_shop3: or did they
10:19 PM aandrew: I'm not sure which approach you're taking. how are you mapping the pins to inputs
10:19 PM aandrew: NORMALLY you don't speify +/-, you say that input pin X is diff and that's it
10:19 PM rue_shop3: NET "diff_n" LOC = F15 ;
10:19 PM rue_shop3: NET "diff_p" LOC = F16 ;
10:19 PM rue_shop3: NET "diff_p" IOSTANDARD = LVDS_33;
10:20 PM rue_shop3: pls tell your method :)
10:20 PM rue_shop3: my module source is
10:20 PM rue_shop3: IBUFDS signal_in_diff(
10:20 PM rue_shop3: .O(led_signal),
10:20 PM rue_shop3: .I(signal_in_p),
10:20 PM rue_shop3: .IB(signal_in_n)
10:20 PM rue_shop3: );
10:20 PM rue_shop3: it wont map
10:20 PM rue_shop3: er
10:20 PM rue_shop3: dambit caopy and past
10:20 PM rue_shop3: my module source is ----
10:21 PM rue_shop3: module main(led1, led3, diff_p, diff_n);
10:21 PM rue_shop3: input diff_p, diff_n;
10:21 PM rue_shop3: output led1;
10:21 PM rue_shop3: output led3;
10:21 PM rue_shop3: // assign led1 = diff_p;
10:21 PM rue_shop3: assign led3 = 1;
10:21 PM rue_shop3:
10:21 PM rue_shop3: IBUFDS signal_in_diff(
10:21 PM rue_shop3: .O(led1),
10:21 PM rue_shop3: .I(diff_p),
10:21 PM rue_shop3: .IB(diff_n)
10:21 PM rue_shop3: );
10:21 PM rue_shop3: endmodule
10:21 PM rue_shop3: --
10:21 PM aandrew: yeah... never like that for me anyway
10:21 PM rue_shop3: ohohohoh
10:21 PM aandrew: let me dig it up but mine will be altera based
10:21 PM rue_shop3: new error
10:21 PM rue_shop3: The I/O components "diff_p" and "diff_n" are the P- and
10:21 PM rue_shop3: N-sides of a differential I/O pair. The component "diff_p" needs to be
10:21 PM rue_shop3: placed in a IOBM site and component "diff_n" in the adjacent IOBS site within
10:21 PM rue_shop3: the same I/O tile. The following issue has been detected:
10:21 PM rue_shop3: All of the logic associated with this structure is locked and the relative
10:21 PM rue_shop3: placement of the logic violates the structure. The problem was found between
10:21 PM rue_shop3: the relative placement of IOB diff_p at site PAD82 and IOB diff_n at site
10:21 PM rue_shop3: PAD81.
10:22 PM rue_shop3: it mapped!!!
10:22 PM rue_shop3: omg omg omg
10:22 PM rue_shop3: being excited about this is SO STUPID
10:23 PM aandrew: set_location_assignment PIN_K15 -to mysig
10:23 PM aandrew: (you don't map the n)
10:23 PM rue_shop3: intersting, in this, you dont set the standard on the n
10:23 PM rue_shop3: it generated!!!!
10:23 PM rue_shop3: OMG
10:23 PM aandrew: set_instance_assignment -name IO_STANDARD LVDS -to mysig
10:24 PM aandrew: you should not have to directly instantiate an LVDS input
10:25 PM rue_shop3: hmm, I wonder if they dont do the ucf thing the same
10:25 PM rue_shop3: ok! its doing something!
10:26 PM rue_shop3: is that at the vhdl level you do that?
10:26 PM rue_shop3: I have one file for the vhdl and one for the pin assignment
10:28 PM aandrew: rue_shop3: no that's in the project file
10:28 PM rue_shop3: hmm
10:28 PM aandrew: (it's called .qpf in altera parlance, but you can do it via GUI too, it all ends up in the .qpf)
10:28 PM aandrew: the VHDL doesn't deal with pin config, only signal names
10:29 PM rue_shop3: root@blackie3:/files/programming/fpga/xilinx/spartin6/LVDS# ls *.qpf
10:29 PM rue_shop3: ls: cannot access '*.qpf': No such file or directory
10:29 PM aandrew: the HDL expects it to be mapped already
10:29 PM rue_shop3: ok
10:29 PM rue_shop3: I dont have one :/
10:29 PM aandrew: yeah like I said, this is altera/intel not Xilinx
10:29 PM rue_shop3: hmm
10:29 PM rue_shop3: ok
10:29 PM aandrew: the xilinx stuff should be VERY similar
10:29 PM aandrew: where is the pin mapping done?
10:29 PM rue_shop3: well, I'm gonna go push in some analog and see what I get :)
10:29 PM aandrew: where you say "signal foo is a LVDS signal and on pin K15" ?
10:30 PM rue_shop3: qmtech.ucf
10:30 PM rue_shop3: NET "diff_p" LOC = F15 ;
10:30 PM rue_shop3: NET "diff_n" LOC = F16 ;
10:30 PM rue_shop3: NET "diff_p" IOSTANDARD = LVDS_33;
10:30 PM rue_shop3: I have to specify both, becaue I have to ...
10:30 PM rue_shop3: root@blackie3:/files/programming/fpga/xilinx/spartin6/LVDS# ls *.qpf
10:30 PM rue_shop3: ls: cannot access '*.qpf': No such file or directory
10:30 PM rue_shop3: no
10:30 PM rue_shop3: IBUFDS signal_in_diff(
10:30 PM rue_shop3: .O(led1),
10:30 PM rue_shop3: .I(diff_p),
10:30 PM rue_shop3: .IB(diff_n)
10:30 PM rue_shop3: );
10:30 PM rue_shop3: ^^ because I ahve to do that
10:30 PM rue_shop3: sorry, the copy/paste on this is being an ass
10:31 PM rue_shop3: .O is the name of the signal resulting from the differential configuration
10:31 PM rue_shop3: but that in the vhdl, so I'm suspect they are just doing it via logic
10:32 PM rue_shop3: but they can also turn on and off the terminating resistor
10:32 PM rue_shop3: so...?
10:32 PM aandrew: set_property IOSTANDARD LVDS_25 [get_ports {MY_LVDS_P}]
10:32 PM aandrew: set_property IOSTANDARD LVDS_25 [get_ports {MY_LVDS_N}]
10:32 PM aandrew: set_property PACKAGE_PIN U12 [get_ports {MY_LVDS_P}]
10:32 PM aandrew: set_property PACKAGE_PIN U11 [get_ports {MY_LVDS_N}]; #this N-side constraint is optional
10:32 PM aandrew: set_property DIFF_TERM TRUE [get_ports {MY_LVDS_P}]; #gives internal termination for LVDS input
10:32 PM aandrew: yeah I don't manually instantiate like that
10:32 PM aandrew: I'd just have something like led <= diff_in;
10:33 PM aandrew: and let it do the inferring
10:33 PM rue_shop3: I'll go see if its actually working, or using logic to do the "differential"
10:33 PM rue_shop3: yea, I like your system
10:35 PM aandrew: you've gotta remember, this isn't a gate you can wire up like you've specified
10:36 PM aandrew: the 'O' of that ibuf can't be connected to another pin
10:36 PM aandrew: it has to feed (at a minimum) the fabric, and make its way to the 'I' of an obuf
10:37 PM aandrew: when you let the system do its job it takes care of that, when you're directly instantiating a block I am not usre
10:38 PM aandrew: now having said all that
10:38 PM aandrew: it seems that perhaps xilinx is different enough:
10:38 PM aandrew: IBUFDS_inst : IBUFDS
10:38 PM aandrew: generic map ( DIFF_TERM => TRUE, -- Differential Termination IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards IOSTANDARD => "DEFAULT")
10:39 PM aandrew: port map ( O => MY_SINGLE_END, -- Buffer output I => MY_LVDS_P, -- Diff_p buffer input (connect directly to top-level port) IB => MY_LVDS_N -- Diff_n buffer input (connect directly to top-level port)
10:39 PM aandrew: );
10:39 PM aandrew: pasted
10:39 PM aandrew: wow that pated shitty
10:44 PM rue_shop3: ok!
10:44 PM rue_shop3: I get 70mV of schmitt!
10:46 PM rue_shop3: it worked directly to the output
10:46 PM rue_shop3: which I'm uncomfortable with, but it worked?
10:46 PM rue_shop3: so, worse, I left it on an led
10:46 PM rue_shop3: so there is some distortion going on
10:46 PM rue_shop3: I'll use another io and see what I get
10:47 PM rue_shop3: I really just wanted to know, when used as a comparator like that, what the schmitt was
10:48 PM Tom_L: progress?
10:48 PM rue_shop3: ..and the range, brb
10:50 PM rue_shop3: aandrew, to be clear, usually .O would be an internal signal
10:50 PM rue_shop3: yes?
10:51 PM rue_shop3: so now I can make an FPGA into a 100 channel ADC?
10:53 PM rue_shop3: I'll try an ADC at some point
10:53 PM rue_shop3: I want to know if I can implement a software RC low-pass
10:53 PM rue_shop3: aandrew, what size are the fpgas you usually work with?
11:01 PM rue_shop3: yea this stucks
11:01 PM rue_shop3: just use an LM393
11:02 PM rue_shop3: I'm seeing 140mV of schmitt in some situations
11:02 PM rue_shop3: and "SDIO" sucks
11:02 PM rue_shop3: as a io standard
11:02 PM rue_shop3: well ok
11:03 PM rue_shop3: now I know!
11:04 PM rue_shop1: :( my scope is still having memory issues
11:41 PM rue_mohr: aandrew, you went poof?