#garfield Logs

Sep 10 2020

07:07 AM polprog: must be big, and clunky
07:13 AM polprog: ideally would have a place for a LOTO tag
12:28 PM polprog: i think the PLL is close to lock... it can properly integrate the output signal
12:29 PM polprog: the error amplifier part is working
12:29 PM polprog: now i need to make it adjust a varicap.. that will be tricky on 5V
12:29 PM polprog: i could power it all with 12V and use a 7805 for the 5V part
01:49 PM polprog: https://polprog.net/rozne1/ircjunk/gal/pll/inphase.jpg
01:49 PM polprog: https://polprog.net/rozne1/ircjunk/gal/pll/outofphase.jpg
01:49 PM polprog: https://polprog.net/rozne1/ircjunk/gal/pll/nearly_in_phase_withCV.jpg this is what i got so far
03:33 PM polprog: hmm i cant get it to sync for no money
03:41 PM polprog: maybe the oscillators i have are too jiterry
03:41 PM polprog: i should test the phase-voltage converter...
03:41 PM polprog: maybe it could sync to a generated signal
03:41 PM polprog: as in, steady generated signal
03:41 PM polprog: no jitter and such
07:29 PM rue_mohr: hmm
07:29 PM rue_mohr: whats the circuit look like?
10:04 PM rue_shop1: Tom_L, vfd?
10:07 PM Tom_L: huh?
10:11 PM Tom_L: measured some signals in the box tonight so i know what i've got to work with for controlling it
10:11 PM Tom_L: i'd forgotten alot of the wiring but i have fair notes
10:27 PM rue_mohr: polprog, my chips from rf arrived
10:27 PM rue_mohr: have you tried his chips yet?
10:56 PM rue_mohr: well I got 7/8 of a row on both pillers done
11:25 PM rue_mohr: ok I have like 20 mins left to live