#garfield Logs

Feb 20 2020

12:06 AM X704 is now known as tiwake
12:13 AM rue_shop1: cool, the winder works nicely for counting turns when unwinding transformers
12:13 AM rue_shop1: 3:3:10:38
03:33 AM X704 is now known as tiwake
03:41 AM X704 is now known as tiwake
04:26 AM polprog: what's the point of knowing the turn count when the transformer's no more after the process :P?
04:27 AM polprog: ive got this indesit branded power supply, ill just take it apart since it uses exotic connectors and stuff
04:27 AM polprog: no documentation and i cant see where the mains goes in
05:21 AM polprog: the 7 segment driver module i have has got a 4 bit bcd input and a latch signal
05:22 AM polprog: at posedge of that latch signal (called dclk) it sets the outputs accordingly
05:22 AM polprog: so im trying to use it with an encoder handler signal now
05:22 AM polprog: and i need to generate taht posedge someway
05:26 AM X704 is now known as tiwake
05:26 AM polprog: https://polprog.net/rozne1/ircjunk/fpga/clocktest.v
05:26 AM Tom_L: morning
05:26 AM polprog: morning
05:27 AM Tom_L: your counter code?
05:27 AM polprog: yeah. i want to make it so that the digit changes as i turn the encoder dial
05:27 AM polprog: im getting an error that a signal is connected to multiple drivers
05:27 AM polprog: dclka signal
05:28 AM Tom_L: https://www.youtube.com/watch?v=o8lezpJhfAo
05:29 AM Tom_L: yours is decimal, not hex though
05:29 AM polprog: and a 3 wire encoder, but the idea is the same
05:29 AM Tom_L: mine is 3 wire
05:29 AM polprog: oh
05:29 AM Tom_L: A B & Z or whatever the index is
05:30 AM Tom_L: just doesn't show the index in that video
05:30 AM polprog: ive never used an encoder before but i know the signal pattern, one way its 00 01 11 10 and the opposite way is backwards
05:31 AM Tom_L: i think rue was working on one too
05:31 AM polprog: i dont know how to make it so that i can write 1 and 0 to that signal respectively
05:34 AM Tom_L: http://tom-itx.no-ip.biz:81/~webpage/temp/xilinx/quadrature/
05:36 AM polprog: hmm
05:40 AM polprog: i think i got it...
05:43 AM polprog: hmm, no
05:44 AM polprog: ive got a module that has an input wire. and i need to drive that wire with something
05:45 AM polprog: maybe my 7 segment display driver is wrong with that latch input
06:16 AM polprog: ok, i give up.
06:16 AM polprog: lets try to use the onboard clock signal for something
06:28 AM polprog: no luck today :(
06:36 AM polprog: all these errors came up when i used that 7 segment module for some reason
07:25 AM X704 is now known as tiwake
09:08 AM rue_mohr: polprog,
09:08 AM rue_mohr: the one I did?
09:14 AM polprog: no, my own implementation
09:14 AM polprog: i dont understand the error message
09:14 AM rue_mohr: k
09:14 AM polprog: also i seem to be able to run ise as normal user
09:15 AM rue_mohr: it hates unused signals
09:16 AM rue_mohr: assign inputs that are unused to high 1'b1 or low 1'b0
09:16 AM polprog: let me try recreate that
09:26 AM polprog: hmm, im getting totally different errorrs now
09:26 AM polprog: im trying to make an as simple as possible encoder handling
09:26 AM rue_mohr: ok, so you have a module with 2 inputs and...?
09:26 AM polprog: ive got a quadrature encoder and i wanna use my 7 sergemtn driver module
09:27 AM rue_mohr: so have the display show 0-3?
09:27 AM polprog: so my top module has input wire[s]: sig1, sig2 and reg[6:0] output display_out
09:27 AM rue_mohr: 0-1-3-2
09:27 AM rue_mohr: ok, you need to tie the other two inputs to something
09:27 AM rue_mohr: like 1'b1
09:27 AM polprog: let me finish
09:27 AM rue_mohr: well specically 1'b0
09:28 AM polprog: no, i wanna make the display go up (or at least for now display '1') if i turn it one way, and go down when i turn the encoder the other way
09:28 AM polprog: give me a sec to find out what this error means and ill show you what i have now
09:28 AM polprog: since the "multpile drivers" error went away
09:28 AM rue_mohr: heh, you didn't notice how long it took me to make that counter?
09:28 AM polprog: i rewrote the code from the morning from scratch
09:28 AM polprog: no, how long?
09:29 AM rue_mohr: like a week and a half
09:29 AM polprog: :-O
09:29 AM rue_mohr: its working, I need to make the encoder interface for it
09:29 AM rue_mohr: but I been distracted with this motor driver project
09:40 AM polprog: Signal latch in unit enc is connected to following multiple drivers
09:42 AM polprog: https://polprog.net/rozne1/ircjunk/fpga/encoder.v
09:43 AM polprog: whats causing that error.. inside the 7 segment module latch is only read
09:44 AM polprog: the module is connected with the top module with a `wire latchw`
09:44 AM polprog: http://paste.debian.net/1131259/
09:45 AM polprog: and how come output signals of the digit reg drive the latch
09:45 AM polprog: thats doesnt make sense to me
09:51 AM polprog: worst thing is this doesnt compile so i cant see the nice logic schematic under the "View Technology Schematic" and see what's wrong
10:14 AM polprog: i think im close
10:14 AM polprog: i need to figure out this latch signal assignment
10:15 AM polprog: since i cant seem to just assign zero to it on negedge and 1 on posedge
10:15 AM polprog: thats where the multiple driver issue comes from...
12:02 PM polprog: Process "Synthesize - XST" completed successfully
12:02 PM polprog: this is good news...
12:20 PM Tom_L: :)
12:33 PM polprog: WOW
12:33 PM polprog: it works
12:33 PM polprog: i just need to hw debounce it
12:33 PM polprog: but it WORKS
12:54 PM polprog: the logic is a bit flawed
01:49 PM polprog: so it detects something
01:49 PM polprog: the numbers change on the display
01:49 PM polprog: but its wrong
07:59 PM rue_bed: ok