#garfield Logs
Feb 04 2020
#garfield Calendar
12:02 AM rue_shop2: yup, as soon as you involve a logic gate it goes to hell
12:07 AM rue_shop2: trying to catch it on itself
12:07 AM rue_shop2: not (led1, redbtn);
12:07 AM rue_shop2: buf (led3, bluebtn);
12:07 AM rue_shop2: it should trip up on that
12:09 AM rue_shop2: wtf
12:09 AM rue_shop2: its their changing the wrong leds
12:10 AM rue_shop2: I think I ahve to start again
12:10 AM rue_shop2: damn, that was like an hour
12:40 AM rue_shop2: ok, I have a working RS latch
12:59 AM rue_shop2: ok nor and nand RS flipflops are working, and D latch is working
12:59 AM rue_shop2: Tom_L, are you interested in following along with these bits?
01:28 AM rue_shop2: ok, 2 bit ripple counter based on T flipflop from D flipflops all good
02:19 AM rue_shop2: ok, I have a working JK flipflop
02:19 AM rue_shop2: no thanks to messed up datasheets
02:21 AM rue_shop2: ok, JK ripple counter is fine
02:33 AM rue_shop2: https://www.electronics-tutorials.ws/wp-content/uploads/2018/05/counter-cou4a.gif
02:37 AM rue_shop2: hahah its counting down
02:48 AM rue_bed: ok, but I fixed it
02:48 AM rue_bed: there isn't much for docs on synchronous JK counters
02:48 AM rue_bed: maybe tommorow I can set up the 74xx279 on the fpga
02:49 AM rue_bed: then I
02:49 AM rue_bed: 'm almost ready for hte encoder
02:49 AM rue_bed: hi zhanx !
02:49 AM rue_bed: satillite internet sucks?
02:50 AM zhanx: yep
03:08 AM rue_bed: got an pc817 opto up to 500khz!
05:02 AM Tom_L: rouge char was a java thing
05:13 AM Tom_L: good you're getting it figured out
05:14 AM Tom_L: the java thing was loosing characters on a file import so i added the '/' or whatever it was ahead of each one that came up missing
05:14 AM Tom_L: and yes i've been waiting to follow along even if i get lost along the way
06:28 AM polprog: heh, interesting
06:28 AM polprog: president harry II cb radio, internal speaker disconnected
06:29 AM polprog: when the radio is supposed to make sound, the power supply current limit hits and the transformer is making noise
06:29 AM polprog: it suffered some heavy water damage
06:29 AM polprog: the TDA2003 is getting pretty warm.
06:30 AM polprog: noise as in radio sounding noise
06:44 AM polprog: weird, goes away when i plug the handpiece in
06:44 AM polprog: i guess its supposed to stay attached
06:44 AM polprog: amazing. the radio starts working fine as soon as i plug the handpiece in
10:17 AM rue_bed: keyswitch
01:35 PM Tom_L: https://www.fpga4student.com/p/fpga-projects.html
01:54 PM rue_shop2: tom, I think the ide loses its brain if its been running too long
01:55 PM rue_shop2: its like its not accepting my modifying the ucf
01:56 PM rue_shop2: restarted it, ...
01:56 PM rue_shop2: no, what the hell
01:57 PM rue_shop2: or maybe there cant be a space before "net"
01:57 PM rue_shop2: nope
01:57 PM rue_shop2: thats not it either
01:57 PM rue_shop2: NET "U8_41" Loc = P5 | IOSTANDARD = SDIO;
01:58 PM rue_shop2: same difinition I been using from the start
01:58 PM rue_shop2: module main(
01:58 PM rue_shop2: input clk
01:58 PM rue_shop2: ,input bluebtn ,input redbtn
01:58 PM rue_shop2: ,output led1 ,output led3
01:58 PM rue_shop2: ,output U8_41 ...
01:58 PM rue_shop2: assign U8_41 = 0 ;
01:59 PM rue_shop2: ConstraintSystem:59 - Constraint <IOSTANDARD = SDIO;> [qmtech.ucf(24)]:
01:59 PM rue_shop2: NET "U8_41" not found. Please verify that:
01:59 PM rue_shop2: 1. The specified design element actually exists in the original design.
01:59 PM rue_shop2: 2. The specified object is spelled correctly in the constraint source file.
02:02 PM rue_shop2: all the io broke
02:04 PM rue_shop2: this makes no sense
02:04 PM rue_shop2: trying an old project
02:23 PM rue_shop2: I think it dies in a strange way when I make combinational circuits
02:49 PM rue_shop2: I fixed it, but I'm not sure what I did
03:21 PM Tom_L: heh
03:22 PM Tom_L: i posted that as some projects to try later
03:24 PM polprog: https://www.fpga4student.com/2016/11/plate-license-recognition-verilogmatlab.html
03:24 PM polprog: wow, thats a beefy FPGA board lol
04:56 PM rue_shop2: hmm, the counter counts down fine
04:56 PM rue_shop2: just not up
04:56 PM Tom_L: one of those projects is an up dn counter
04:57 PM rue_shop2: and does not have an asynchronous reset
04:57 PM rue_shop2: because nobody seems to know how to do that
04:57 PM rue_shop2: no less a decade one
04:57 PM rue_shop2: and not with seperate up and down clock lines
04:58 PM rue_shop2: I"m determined to make this work the way it should
05:00 PM Tom_L: day off today?
05:00 PM rue_shop2: snow
05:00 PM rue_shop2: well, LOTs of slush
05:00 PM Tom_L: yeah we had slush one day
05:01 PM Tom_L: the one day i had lots of travel to do
05:01 PM polprog: an asynchronous counter is one of the things ill be implementing on an fpga eventually
05:01 PM Tom_L: sooner than later polprog
05:01 PM Tom_L: :)
05:01 PM polprog: :P
05:01 PM polprog: i hope so, if the project doesnt fall out
05:02 PM rue_shop2: so, I'm building a 74ls192 without the load ability
05:02 PM rue_shop2: but it looks like the diagrams for that chip have a subtle error in them
05:02 PM Tom_L: firing up the webpack pc...
05:02 PM polprog: webpack pc?
05:02 PM Tom_L: my main pc
05:03 PM rue_shop2: yea, there is an error here somehow
05:05 PM Tom_itx: https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/design-software/vhdl/vhd-counter-synch.html
05:08 PM Tom_itx: https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/design-software/verilog/ver-counter.html
05:08 PM Tom_itx: verilog version
05:09 PM rue_shop2: not up down decimal
05:09 PM rue_shop2: I"m telling you, nobody in the hisotry of fpgas has done this
05:09 PM Tom_L: that's a bold statement
05:09 PM Tom_L: you want binary?
05:11 PM Tom_L: oh, bcd
05:11 PM rue_shop2: yea
05:11 PM rue_shop2: bcd, seperate up and down clocks, with async reset
05:13 PM rue_shop2: I didn't want to learn how it works, I just wanted to set one up
05:13 PM Tom_itx: https://surf-vhdl.com/how-to-implement-a-bcd-counter-in-vhdl/
05:13 PM rue_shop2: bet its not up/down
05:13 PM Tom_L: probably not
05:14 PM rue_shop2: with seperate up/down clocks
05:14 PM Tom_L: what's the need for separate clocks?
05:14 PM rue_shop2:
05:14 PM rue_shop2: and G15(og15, ~clkup, u1q, u2q );
05:14 PM rue_shop2: and G16(og16, u2qn, u1qn, ~clkdown, og18);
05:14 PM rue_shop2: nor G17(og17, og15, og16 );
05:14 PM rue_shop2:
05:14 PM rue_shop2: there is an error in this area, and I dont know what it is yet, but its not my translation
05:15 PM rue_shop2: its cause of how I"m going to do the encoder
05:17 PM rue_shop2: its got me becasue this should not be a issue
05:17 PM rue_shop2: but verilog cant handle events on multiple edges
05:17 PM rue_shop2: (in a good way)
05:23 PM rue_shop2: I might be better off making a big mean state machine
05:24 PM rue_shop2: all I know is that the schematics for the 74ls192 back from god-knows have an error
05:25 PM rue_shop2: https://www.electronics-tutorials.ws/wp-content/uploads/2018/05/counter-cou4a.gif
05:26 PM rue_shop2: thats for a binary
05:26 PM rue_shop2: even finding that is a challange
05:50 PM rue_shop2: I took a look at the implementation, it uses a LUT FSM anyhow
05:51 PM rue_shop2: but its baffling me why this doesn't work
05:51 PM rue_shop2: I didn't 'wire the leds' wrong
05:51 PM rue_shop2: counting down works, and the other counters work
05:52 PM rue_shop2: its like the carry mechanism is breaking the count
05:52 PM rue_shop2: tom
05:52 PM rue_shop2: https://paste.debian.net/1129197/
05:52 PM rue_shop2: thats where I"m at now
05:53 PM rue_shop2: I'd just commented out 129, it works
05:53 PM rue_shop2: I'm trying to get 127 to work
05:54 PM rue_shop2: on 3, it lights up the 3rd bit, and then it just stays stuck on
05:55 PM rue_shop2: actually, due to the verilog limitations, I cant make a big fsm
05:56 PM rue_shop2: it wont let me or 3 signals togethor and do an edge based on them
05:56 PM rue_shop2: well, hmm, it complains severly anyhow
05:57 PM rue_shop2: I dont want to give in, I'm so close
06:00 PM rue_shop2: oh odd, its doing that ucf thing again
06:01 PM * Tom_L finally sits down for a min
06:02 PM rue_shop2: it says none of the nets are defined
06:02 PM rue_shop2: it did this to me before
06:04 PM Tom_L: are you using an outside editor, their editor or their floorplan area?
06:04 PM rue_shop2: yea, it just freaked out
06:04 PM rue_shop2: no
06:04 PM rue_shop2: its editor
06:04 PM Tom_L: never had a problem with that here
06:04 PM rue_shop2: remember the file you completely rewrote?
06:04 PM rue_shop2: cause it was doing something strange
06:04 PM rue_shop2: ?
06:05 PM Tom_L: which file?
06:05 PM Tom_L: the ucf?
06:05 PM rue_shop2: maybe I'm relying on you to remember
06:05 PM Tom_L: for mine using your names?
06:05 PM rue_shop2: you didn't know why
06:05 PM rue_shop2: but it worked after you redid it
06:05 PM rue_shop2: I didn't change my ucf
06:05 PM rue_shop2: but its saying none of my nets are defined
06:06 PM rue_shop2: I'v ctrl-z'd my way back to what was working, and its still barfing
06:07 PM Tom_itx: is the pastebin current?
06:07 PM rue_shop2: no, I'd commented out the active line
06:07 PM rue_shop2: and I'v made 20 changes since I'd pasted it
06:08 PM rue_shop2: then I ctrl-z'd to before that paste
06:08 PM rue_shop2: ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = SDIO;> [qmtech.ucf(33)]:
06:08 PM rue_shop2: NET "U8_59" not found. Please verify that:
06:08 PM rue_shop2: 1. The specified design element actually exists in the original design.
06:08 PM rue_shop2: 2. The specified object is spelled correctly in the constraint source file.
06:08 PM Tom_itx: paste both files
06:08 PM rue_shop2: its doing that for every net
06:08 PM rue_shop2: for no reason
06:08 PM Tom_itx: and i'l make a project
06:08 PM rue_shop2: https://paste.debian.net/1129200/
06:09 PM rue_shop2: tatsh the ucf, and its fine
06:09 PM rue_shop2: https://paste.debian.net/1129201/
06:09 PM rue_shop2: tahts main.v and its fine, but I get those errors
06:12 PM Tom_L: you got a different chip than mine
06:12 PM Tom_L: is yours x9?
06:12 PM Tom_L: 256
06:12 PM rue_shop2: mine is 256
06:12 PM Tom_L: x9 or x16?
06:12 PM Tom_L: ftg256
06:13 PM rue_shop2: ftg256 yes
06:13 PM rue_shop2: it did this to me before
06:13 PM rue_shop2: I think the combinational logic loops severly mess it up
06:14 PM rue_shop2: it doen't fail till its trying to generate the program file
06:14 PM Tom_L: are you using all the uncommented pins in the pin file?
06:15 PM Tom_L: cause it doesn't look like you are
06:15 PM rue_shop2: ah it went this time
06:15 PM rue_shop2: nope, but I have assigns to take care of them
06:15 PM Tom_L: well i'm getting warnings about a bunch of htem
06:15 PM rue_shop2: Synch4bitDecadeUD <-- right now I have that module commented out and its able to compile it
06:16 PM Tom_L: and errors
06:16 PM rue_shop2: its funny, I started this to play with state machines, and now that I have a chance to do this as a state machine, I'm not doing it
06:17 PM Tom_L: part of it is, you need to define all the IO in the top module () even if it doesn't use them
06:17 PM rue_shop2: but the state machines need an event clock, and I dont really have one for them
06:17 PM Tom_L: it's like an external declaration in c i think
06:17 PM rue_shop2: I did
06:17 PM rue_shop2: 21 thru 39 are commented out
06:18 PM Tom_L: module ttl72
06:18 PM rue_shop2: 41 thru 59 are in the top level, and are set to a dummy value at in there
06:18 PM rue_shop2: sure, what of it...
06:18 PM Tom_L: 41 is in the middle of a module
06:19 PM Tom_L: we are not on the same line numbers
06:19 PM rue_shop2: no
06:19 PM rue_shop2: which line?
06:19 PM Tom_L: i pasted your file and compiled it
06:19 PM Tom_L: as is
06:19 PM rue_shop2: well, its working now
06:19 PM Tom_L: and you say you commented things out
06:20 PM rue_shop2: I commented out the Synch4bitDecadeUD, compiled, it worked, then uncommented it, and its still working
06:20 PM rue_shop2: so, its all working now
06:20 PM rue_shop2: !?!?!?!
06:22 PM Tom_itx: line 32 port size mismatch
06:22 PM Tom_itx: same with 33
06:22 PM rue_shop2: right, I keep using 1 instead of 1'b1
06:23 PM Tom_itx: Formal port size is 1-bit while actual signal size is 32-bit
06:23 PM rue_shop2: right, I keep using 1 instead of 1'b1
06:23 PM Tom_itx: u1qn is never used
06:23 PM rue_shop2: thats ok
06:23 PM Tom_itx: u2q is never used
06:24 PM Tom_itx: u2qn
06:24 PM rue_shop2: wait
06:24 PM rue_shop2: of which module!
06:24 PM Tom_itx: line 32 33
06:24 PM rue_shop2: my line numbers are different
06:25 PM rue_shop2: synch2bitBin?
06:25 PM Tom_itx: they should be the same, you just gave it to me !
06:25 PM Tom_itx: yes
06:25 PM Tom_itx: synch2bit
06:25 PM Tom_itx: the one above the one you said
06:25 PM rue_shop2: there is no u2qn in 2 bit
06:25 PM Tom_itx: module Synch2bit( input clr, input clk, output [1:0] q);
06:25 PM Tom_itx: TTL72 U1 (1, clr, clk, 1, 1, q[0], u1qn);
06:25 PM Tom_itx: TTL72 U2 (1, clr, clk, q[0], q[0], q[1], u2qn);
06:25 PM Tom_itx: endmodule
06:25 PM rue_shop2: er, u2q
06:26 PM rue_shop2: there are 2 qn's that aren't
06:26 PM rue_shop2: thats ok
06:26 PM Tom_itx: typo
06:26 PM rue_shop2: whew
06:26 PM rue_shop2: my problem is with u3q of synch4bitdecadeUP
06:26 PM rue_shop2: my problem is with u3q of synch4bitdecadeUD
06:26 PM rue_shop2: thought you had me a clue!
06:27 PM Tom_itx: clkdown_25 _26 _27 are unconnected in block main
06:27 PM rue_shop2: yea, extra divider bits
06:28 PM rue_shop2: 24 is a nice pace, more division is just patience testing
06:28 PM Tom_itx: The signal U8_51_OBUF has no driver. PAR will not attempt to route this signal.
06:28 PM Tom_itx: 55 57 59 also
06:28 PM Tom_itx: and redbtn
06:29 PM Tom_itx: There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
06:29 PM Tom_itx: There are 4 sourceless signals in this design. This design will not pass the DRC check run by Bitgen.
06:30 PM Tom_itx: you should eliminate a few of those if you expect it to work right
06:31 PM Tom_itx: i get errors
06:32 PM Tom_itx: U8_51_OBUF> is incomplete. The signal is
06:32 PM Tom_itx: not driven by any source pin in the design.
06:32 PM Tom_itx: same with 49 55 57
06:34 PM Tom_itx: ok i took those out of the pin file and now i'm down to 2 warnings and no errors
06:36 PM Tom_itx: removed redbtn for now too
06:36 PM Tom_itx: 9 warnings now
06:48 PM rue_mohr: oh sounds like I missed an assign
06:49 PM Tom_L: soemthing about led1 led3 too
06:50 PM rue_mohr: probably forgot assigns for them
06:51 PM rue_mohr: http://ruemohr.org/~ircjunk/tempimage/p1150074.jpg
06:51 PM rue_mohr: there is the circuit for the up/down counter
06:51 PM rue_mohr: I think its got an error
06:51 PM rue_mohr: BUT
06:51 PM rue_mohr: there are two types of JK flipflops
06:51 PM rue_mohr: nor based, and nand based
06:52 PM rue_mohr: THAT said, I could use the 7474s as flipflops
06:52 PM rue_mohr: I didn't end up needing the JK
06:55 PM Tom_L: but,
06:55 PM Tom_L: are we having fun yet?
06:56 PM rue_mohr: haha, I'm sitting here wondering what productive thing I was supposed to be doing
06:56 PM Tom_L: well, as long as i am sitting here i don't worry about that
06:57 PM rue_mohr: I really could do this with a state machine
06:57 PM rue_mohr: its a heavy one to design tho
06:59 PM rue_mohr: 512 lines
07:00 PM rue_mohr: well, 256 of them are simple... I think
07:00 PM Tom_itx: sounds like it's halfway written
07:09 PM Tom_L: did they patch the road?
07:10 PM rue_mohr: they need to reconstruct the reveene first
07:10 PM rue_mohr: its washed away
07:10 PM rue_mohr: maybe about...
07:11 PM Tom_L: sounds like the whole thing could go
07:11 PM rue_mohr: 96000 cubic feet?
07:12 PM rue_mohr: https://www.coastreporter.net/news/local-news/roberts-creek-roads-hit-by-major-washouts-1.24066673
07:13 PM rue_mohr: the one with the gas main that has the ashfault on it
07:13 PM rue_mohr: they upgraded the cone
07:14 PM rue_mohr: https://www.coastreporter.net/news/local-news/updated-evacuations-ordered-in-roberts-creek-as-flood-damage-worsens-1.24067067
07:14 PM rue_mohr: thats the bottom side of that washout
07:15 PM Tom_itx: looks kinda like california
07:15 PM Tom_itx: they get washouts all the time
07:16 PM rue_mohr: heh, that house, 2022, thats on a $1M lot
07:16 PM Tom_itx: was
07:17 PM rue_mohr: all 'cause one guys driveway colvert plugged and overflowed
07:17 PM rue_mohr: partly cause they didn't put a big-enough one in
07:18 PM Tom_L: they don't have code for that up there?
07:18 PM rue_mohr: partly cause they have to pay for it, the town/highways dosn't
07:18 PM rue_mohr: yea, you ahve to pay and put in your own damn colvert
07:18 PM Tom_L: the county goes around clearing the roadsides on rural roads here
07:18 PM rue_mohr: yea, they knock big rocks into peoples culverts
07:50 PM rue_shop2: ok, I'm restarting like this...
07:50 PM rue_shop2: https://paste.debian.net/1129206/
07:50 PM rue_shop2: see what stops me
07:53 PM Tom_L: what is og1
07:53 PM Tom_L: undefined
07:53 PM rue_shop2: ? they allow you to make it up on the fly as a wire
07:53 PM rue_shop2: which is spooky,
07:54 PM Tom_L: i would list it for sanity
07:54 PM Tom_L: personally
07:54 PM rue_shop2: cause if you make a typo, it just creates a flapping signal with that name
07:54 PM Tom_L: and
07:55 PM Tom_L: since you're using that as a clock source it will get picky where you put it
07:55 PM rue_shop2: oh yea it dosn't like that
07:55 PM rue_shop2: its eating it, but its complaining
07:55 PM Tom_L: and i haven't figured all that out yet
07:55 PM rue_shop2: I have to do it to mix all the signals I need for when the state machine gets evaluated
07:55 PM Tom_L: where clock pins etc are located
07:55 PM Tom_L: or in banks or whatever
07:56 PM Tom_L: i think it bitches if you cross over banks
07:58 PM rue_shop2: its building it all into a state machine anyhow
07:58 PM rue_shop2: I took a peak
07:59 PM rue_shop2: https://paste.debian.net/1129208/
07:59 PM rue_shop2: I'm just about coding as fast as it can compile ya know
07:59 PM Tom_L: heh
08:00 PM Tom_L: so i got a question
08:00 PM rue_shop2: ok, ok, good so far
08:00 PM Tom_L: if <= is assignment, how do you show less than or equal to
08:01 PM rue_shop2: hahah, no idea...
08:01 PM Tom_L: :)
08:01 PM rue_shop2: =< ?
08:02 PM Tom_itx: Relational: < <= > >=
08:02 PM Tom_L: maybe it's in context
08:02 PM rue_shop2: it says that I should use chip enable instead of xoring all my signals, do you know anyhting about that one?
08:05 PM Tom_itx: https://link.springer.com/content/pdf/bbm%3A978-3-642-45309-0%2F1.pdf
08:05 PM Tom_L: i'm not sure
08:05 PM Tom_L: search 'enable'
08:05 PM rue_shop2: maybe later
08:05 PM rue_shop2: I'm thinking about that motor driver
08:05 PM rue_shop2: I didn't expect so much speed out of the opto
08:06 PM Tom_itx: case (count)2, 5, 8, 11 : ena_in <= 1;default : ena_in <= 0;endcase
08:06 PM Tom_L: i'm still not sure
08:08 PM rue_shop2: ooo complex, hmmm
08:08 PM rue_shop2: my idea just hit a brick wall
08:08 PM rue_shop2: I need the state machine
08:08 PM rue_shop2: but xoring all the signals worked
08:10 PM Tom_L: there's probably stuff in that pdf you might be interested in
08:11 PM Tom_itx: if (reset) begin // Asynchronous resetcount <= 0;d <= delta;end else begin
08:12 PM Tom_L: more the construct than the code
08:12 PM rue_shop2: but "you cant have multiple drivers for one signal"
08:12 PM Tom_L: no you can't
08:13 PM rue_shop2: so, if you have a block like that to set a register to 0, you cannot have another one that makes it count
08:13 PM Tom_L: unless you run it thru an OR
08:13 PM rue_shop2: outting always @ (lksd or skdjf or ksjdf) is really hit-and-miss
08:14 PM rue_shop2: the other way I was trying it just refused
08:16 PM Tom_itx: http://cva.stanford.edu/people/davidbbs/classes/ee108a/winter0607%20labs/Building%20Counters%20Veriog%20Example.pdf
08:16 PM rue_shop2: always @ (posedge og1 or negedge og1)
08:16 PM rue_shop2: will it do that?
08:16 PM Tom_L: i don't think so
08:17 PM rue_shop2: I dont eitehr
08:17 PM Tom_L: i tried that once on something
08:17 PM Tom_L: always @(og1)
08:17 PM Tom_L: might get both
08:17 PM rue_shop2: isn't that level too?
08:17 PM Tom_L: i dunno, probably
08:18 PM rue_shop2: inteseting.. its not barfing
08:18 PM Tom_itx: https://www.reddit.com/r/FPGA/comments/44dlbl/verilog_always_block_triggered_on_rising_and/
08:18 PM Tom_itx: says it might
08:19 PM rue_shop2: huh, it took it, but
08:19 PM Tom_L: if you go about it right
08:19 PM rue_shop2: I dont think its actually working
08:19 PM Tom_L: look at the fix for that post
08:20 PM Tom_L: it's not recomended
08:22 PM rue_shop2: it was still counting at the same speed, so I'm sure that altho it did it, it didn't work
08:22 PM rue_shop2: https://paste.debian.net/1129212/
08:24 PM rue_shop2: wow that totally didn't work
08:24 PM rue_shop2: so, it ultimitly rejects it
08:24 PM Tom_L: yeah even if you get past synthesis i think it would fail
08:24 PM Tom_L: i tried
08:25 PM rue_shop2: well, its taking it, just not doing it
08:25 PM rue_shop2: always @ (og1 )
08:25 PM rue_shop2: trying that
08:26 PM Tom_itx: or maybe always@(*)
08:26 PM rue_shop2: if it works, the count rate will double
08:27 PM rue_shop2: nope its just locked again
08:28 PM Tom_itx: https://class.ece.uw.edu/371/peckol/doc/Always@.pdf
08:28 PM rue_shop2: ok, I'll bite on that one
08:28 PM Tom_L: heh
08:29 PM rue_shop2: tho seeing as I have logic, I'll make an edge detector
08:30 PM Tom_itx: Never use<=(non-blocking) assignments inalways@( * )blocks.
08:31 PM rue_shop2: ?
08:31 PM Tom_itx: 1.5
08:31 PM Tom_itx: P2
08:31 PM rue_shop2: k I'm trying soemthing first..
08:31 PM rue_shop2: silly browser didn't open it
08:31 PM Tom_itx: * i think detects change
08:32 PM Tom_itx: so the always@( * ) would detect both edges but you can't specify the source in that header
08:37 PM rue_shop2: anytime I use both edges it just locks up
08:37 PM Tom_L: because they are trying to happen at the same time
08:37 PM Tom_L: you are thinking sequential but it is not
08:37 PM rue_shop2: there is only one signal changing
08:38 PM Tom_L: i wonder if you could have 2 modules
08:38 PM Tom_L: always@(posedge x) begin end
08:39 PM Tom_L: always@(negedge y) begin end
08:39 PM rue_shop2: no that both set the counter
08:39 PM rue_shop2: see why this is so funkey?
08:39 PM Tom_L: it is a problem.
08:39 PM rue_shop2: it ALMOST worked with the logic gate thing
08:39 PM rue_shop2: but there is some kinda error when it hits 3
08:39 PM Tom_L: i'm sure this isn't the first time it's come up
08:40 PM rue_shop2: *when counting up*
08:40 PM rue_shop2: when its counting down, it works fine
08:46 PM rue_shop2: so, for the floating drive supply for the top side fet on the motor driver
08:47 PM rue_shop2: I'm somewhere between using a charge pump, and a coil off a transformer that makes AC for everyones floating drivers
08:47 PM rue_shop2: thoughts?
08:47 PM Tom_L: you're using P channel?
08:47 PM rue_shop2: N
08:48 PM rue_shop2: top and bottom
08:48 PM Tom_L: where's that schematic rif had
08:48 PM rue_shop2: he used a HIP4081
08:48 PM Tom_L: yeah
08:48 PM rue_shop2: that used a charge pump
08:49 PM rue_shop2: with the output
08:49 PM rue_shop2: but
08:49 PM rue_shop2: its not good at 100% duty
08:50 PM Tom_itx: http://www.verilog.renerta.com/source/vrg00014.htm
08:51 PM Tom_L: meh, i dunno
08:51 PM Tom_L: was just reading to see if i could find something
08:53 PM rue_shop2: drat, I dont want clocks all over the place
08:53 PM Tom_itx: If an input is declared as a vector port then the least significant bit is used to detect the edge transition. If no transition is specified, then the edge sensitive path works as a simple module path (i.e. at any transition that occurs on an input terminal).
08:54 PM rue_shop2: otherwise I'm gonna have to pass a high freq clock to EVERYTHING
08:56 PM Tom_L: my eyes are tired.
08:57 PM rue_shop2: yea, I'm gettin there
08:57 PM rue_shop2: I should start supper
09:20 PM rue_shop2: nope I dont think I can
09:22 PM rue_shop2: ok, for now its beat me
09:22 PM rue_shop2: but only just barely
09:24 PM rue_shop2: an fsm has to be clocked
09:24 PM rue_shop2: and if my clocks are limited to the signals that are going into the fsm, and I cant have dual edge execution, I'm screwed
09:24 PM rue_shop2: I'd have to put a full on sample clock into it
09:25 PM rue_shop2: but, last I looked, I cant make a signal global
10:48 PM Tom_L: why is it necessary you have 2 clocks for this?