#garfield Logs
Feb 01 2020
#garfield Calendar
01:23 AM rue_shop2: oh, hmm
01:29 AM rue_shop2: the # delay things?
01:29 AM rue_shop2: I think their just for simulation
04:01 AM Tom_L: no
04:02 AM Tom_L: i don't think so i think # will work in hardware too
04:03 AM Tom_L: http://www.verilog.renerta.com/source/vrg00011.htm
04:05 AM Tom_L: but why would you need a delay?
04:24 AM rue_shop2: wow geez
04:24 AM rue_shop2: the bidir counter really beat me up
04:24 AM rue_shop2: so the clock edge comes into the counter
04:25 AM rue_shop2: I have to come up with the next value, and work out if it was up or down
04:25 AM rue_shop2: everyone has counters with up/down control and a clock
04:25 AM rue_shop2: but I want two clocks, one for up, the other for down
04:26 AM rue_shop2: and thats not pretty
04:27 AM rue_shop2: so, I have one register that latches the next value up, and one that latches the next value down
04:27 AM rue_shop2: I use a selector to work out which one to output
04:27 AM rue_shop2: and I use an RS flipflop to work out which pulse was the last valid one
07:02 AM Tom_L: you can do that with one clock
07:02 AM Tom_L: count up with on var and down with the other
07:21 AM Tom_L: 2 clocks seems like a waste of resources to me
12:43 PM rue_mohr: no
12:43 PM rue_mohr: I want it done with 2 clocks
12:43 PM rue_mohr: it shouldn't need a bunch of resources
12:43 PM rue_mohr: but the fpga constraints are being annoying
03:21 PM Tom_L: i don't follow quite what you're doing with the 2 clocks
03:21 PM rue_mohr: counter
03:21 PM rue_mohr: one clock makes the count go up, the other makes the count go down
03:21 PM Tom_L: one for each channel
03:22 PM rue_mohr: still needs the encoder interface
03:23 PM Tom_L: mmm
03:36 PM Tom_L: i should adjust it for my pin file so i can follow along
03:43 PM Tom_L: can you tell me the segment order from U8_41...U8_59?
03:43 PM Tom_L: not all of those are segments i doubt
03:44 PM Tom_L: also the anode/cathode lines
03:44 PM Tom_L: and where you're putting the encoder
03:49 PM Tom_L: anyway.. bak in a while
05:44 PM polprog: https://polprog.net/rozne1/ircjunk/secret.wav
05:48 PM Tom_L: what's up?
05:49 PM polprog: not much
05:49 PM polprog: done studying
05:49 PM polprog: exams on monday
05:49 PM polprog: now playing with sstv as you can see
05:49 PM Tom_L: was gonna ask if you passed
05:50 PM Tom_L: nothing to watch/play that on on this pc
05:50 PM polprog: hmm
05:50 PM polprog: i found SDR apps on adnoid be pretty okay
05:50 PM polprog: not as great as gqrx but the mobility is amazing
05:52 PM polprog: i dunno byt the sstv sounds are pretty pleasant
05:52 PM polprog: scottie 1 sounds just like dialup
05:53 PM polprog: SSTV sounds like fun tbh
06:19 PM Tom_L: well i guess rue doesn't wanna play tonight
07:30 PM rue_shop2: ?
07:30 PM rue_shop2: have you seen a method of doing a 'pullup' in verilog?
07:33 PM rue_shop2: in verilog, do I need a resistor, or can I just set a signal to 1?
07:33 PM rue_shop2: :)
07:39 PM Tom_L: you can do it in the planner
07:39 PM Tom_L: one sec
07:49 PM Tom_L: there?
07:50 PM rue_shop2: I think I'm ok
07:50 PM rue_shop2: it would be nice to be able to set up a default value for unconnected nets
07:51 PM Tom_L: under User Constraints, launch Floorplay Area/IO Logic (Planahead)
07:51 PM Tom_L: set them with that utility
07:52 PM Tom_L: although i just ran it to test and don't see any 'pullup' keyword listed in the ucf file
07:53 PM Tom_L: ahh, yes it added it to the bottom
07:53 PM rue_shop2: module FF74xx74(input set, input clr, input clk, input d, output q, output qn);
07:53 PM rue_shop2: wire g3o, g4o, g5o, g6o;
07:53 PM rue_shop2:
07:53 PM rue_shop2: nand G1 ( q, set, g4o, qn );
07:53 PM rue_shop2: nand G2 ( qn, clr, g5o, q );
07:53 PM rue_shop2: nand G3 ( g3o, set, g6o, g4o);
07:53 PM rue_shop2: nand G4 ( g4o, clr, clk, g3o);
07:53 PM rue_shop2: nand G5 ( g5o, g4o, clk, g6o);
07:53 PM rue_shop2: nand G6 ( g6o, clr, d, g5o);
07:53 PM rue_shop2: endmodule
07:53 PM Tom_L: so:
07:53 PM rue_shop2: asynchronous set and clear
07:54 PM rue_shop2: now I need to make a up/down counter with it
07:54 PM Tom_itx: /quadrature A
07:54 PM Tom_itx: NET "quadA" LOC = P41;
07:54 PM Tom_itx: NET "quadA" IOSTANDARD = LVCMOS33;
07:54 PM Tom_itx: /quadrature b
07:54 PM Tom_itx: NET "quadB" LOC = P35;
07:54 PM Tom_itx: NET "quadB" IOSTANDARD = LVCMOS33;
07:54 PM Tom_itx: # PlanAhead Generated IO constraints
07:54 PM Tom_itx: NET "quadB" PULLUP;
07:54 PM Tom_itx: NET "quadA" PULLUP;
07:55 PM Tom_L: you can likely put that all on one line per pin
07:55 PM rue_shop2: huh, is that the ucf or the v ?
07:55 PM Tom_L: ucf
07:55 PM rue_shop2: yea, I'm talking in the verilog
07:55 PM Tom_L: it's physical pins not virtual
07:55 PM Tom_L: none i'm aware of
07:55 PM rue_shop2: ^^^ I'd like that 74xx74 module to have a default for unconnecteds
07:56 PM Tom_itx: https://verificationacademy.com/forums/systemverilog/usage-pullup-and-bufif0-switch-level-modelling-constructs-verilog
07:56 PM Tom_itx: https://www.xilinx.com/support/answers/3377.html
07:57 PM Tom_L: so, yes you can
07:57 PM rue_shop2: I dont know what to trust after that delay thing isn't real
07:57 PM Tom_L: are they defined as wires?
07:58 PM rue_shop2: ... scroll up...
07:58 PM rue_shop2: go on...
07:58 PM Tom_L: so then read that first link
07:58 PM rue_shop2: yea, they dont use it the same and I dont know if I should trust it
07:59 PM rue_shop2: oh it hilights
08:00 PM Tom_itx: https://web.stanford.edu/class/ee183/handouts_win2003/VerilogQuickRef.pdf
08:00 PM Tom_itx: search for 'pullup' and note the different applications
08:00 PM Tom_L: one should apply
08:00 PM rue_shop2: ERROR:Xst:850 - "/files/programming/fpga/xilinx/spartin6/7seg_pt1/main.v" line 73: Unsupported Switch or User Defined Primitive.
08:00 PM rue_shop2: nope
08:01 PM Tom_L: why not at the pin file level?
08:01 PM rue_shop2: tho, I would think there is a way to do it with a wired or , or wired and
08:02 PM rue_shop2: because its not a pin
08:02 PM rue_shop2: its an internal signal that I may not use
08:02 PM rue_shop2: ttl has pullups
08:02 PM rue_shop2: if you dont connect something
08:03 PM Tom_itx: http://verilog.renerta.com/mobile/source/vrg00003.htm
08:05 PM rue_shop2: the # delays aren't real
08:05 PM rue_shop2: so ignore all that
08:05 PM Tom_L: mkay
08:05 PM Tom_L: can you assign it as a gate instead of a wire?
08:05 PM Tom_itx: http://www.asic-world.com/verilog/gate1.html
08:06 PM rue_shop2: ooo tristate stuff
08:08 PM Tom_itx: https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/design-software/verilog/ver_tristate.html
08:08 PM Tom_L: seems that bufif is a keyword in making it work
08:11 PM Tom_L: # does introduce a delay however...
08:11 PM Tom_itx: SEQUENTIAL STATEMENTS: execute in order specified by algorithm and delimited by begin/end.begin/* enter block at time T */#10 a = 0; /* a changes to 0 at time T+10 */#10 a = 1; /* a changes to 1 at time T+20 */end
08:11 PM Tom_L: lost the formatting in the paste
08:12 PM rue_shop2: no, the delay is not real
08:12 PM rue_shop2: you cannot use it on an fpga => therefore its not real
08:12 PM rue_shop2: its for simulation
08:12 PM rue_shop2: }:| it didn't help me any
08:13 PM Tom_L: i'm not sure if i agree or disagree at this point
08:13 PM rue_shop2: make a real thing and run it that tries to use the delay
08:13 PM rue_shop2: it wont work
08:13 PM Tom_L: it won't delay a thing x clock cycles?
08:14 PM rue_shop2: nope
08:14 PM Tom_L: did you verify that on a logic analyser etc?
08:14 PM rue_shop2: I tried to use it to mix edge signalling
08:14 PM rue_shop2: I'm done with it, I'v written it off
08:14 PM rue_shop2: you play if you like :)
08:17 PM Tom_L: meh
08:17 PM Tom_L: i haven't used it yet
08:17 PM Tom_L: is why i'm unsure
08:19 PM Tom_itx: not to beat it to death but i did find this: https://www.chipverify.com/verilog/verilog-gate-delay
08:19 PM rue_shop2: its not real
08:20 PM Tom_L: ok
08:20 PM rue_shop2: I dont even want to look into it now, cause everything I did last night, for hours, proved its just a simulation thing
08:20 PM rue_shop2: I was really annoyed
08:20 PM rue_shop2: cause I wanted to produce a pulse when an event happened
08:21 PM rue_shop2: I'm moving on without it
08:21 PM rue_shop2: I have made a 74ls74 flipflop
08:21 PM rue_shop2: and I can use that to make a 74ls192 bidir counter
08:21 PM Tom_L: fair enough
08:22 PM rue_shop2: which will take me a while
08:23 PM Tom_L: point is... are we having fun yet?
08:23 PM rue_shop2: heh
08:23 PM rue_shop2: 19 gates and 4 flipflops
08:24 PM rue_shop2: all because there seems to be no other way to do two counter clocks (one for up, one for down) and asynchronous set/reset in verilog
08:24 PM Tom_L: i should make a pin file to keep up with yours so the board io do the same thing
08:24 PM rue_shop2: :)
08:25 PM rue_shop2: so far I just have the display
08:25 PM Tom_L: you should add // 7seg - seg A etc to your file and post it so i can mod mine
08:25 PM rue_shop2: hmm
08:26 PM rue_shop2: I'll do that as I go
08:26 PM Tom_L: i've pretty well added most of the io on mine in a file and just comment out what i don't need
08:26 PM rue_shop2: its too bad you cant give a pin multiple names
08:26 PM Tom_L: so far you got clock, bluebtn, redbtn, 7seg A-G and anodes iirc
08:27 PM Tom_L: and whatever you've added
08:27 PM rue_shop2: sounds like your prettymuch good
08:27 PM rue_shop2: I have to get this counter working, then I can make the front end for the encoder
08:27 PM Tom_L: no that's from memory, i don't have the file pinout
08:27 PM rue_shop2: than it'll just work
08:33 PM rue_shop2: FF74xx74 D0 (1, ~rst, clkup, d0qn, q[0], d0qn);
08:33 PM rue_shop2: FF74xx74 D1 (1, ~rst, q[0], d1qn, q[1], d1qn);
08:33 PM rue_shop2: FF74xx74 D2 (1, ~rst, q[1], d2qn, q[2], d2qn);
08:33 PM rue_shop2: FF74xx74 D3 (1, ~rst, q[2], d3qn, q[3], d3qn);
08:33 PM rue_shop2: ??? chain or T flipflops as a test...
08:35 PM rue_shop2: w... t... f....
08:39 PM rue_shop2: tom, this is not the first time this has come up
08:40 PM rue_shop2: it LOOKS like all the bits are inverted?
08:40 PM Tom_L: iirc fpga use negative logic if that makes sense
08:41 PM Tom_L: i know on my mill i gotta reverse everything when i go direct to the fpga instead of buffered io
08:41 PM rue_shop2: that expalians the RS flipflop last night too
08:41 PM rue_shop2: I made
08:41 PM rue_shop2: module RSFF(input r, input s, output q, output qn ) ;
08:41 PM rue_shop2:
08:41 PM rue_shop2: nor G1 (q, r, qn);
08:41 PM rue_shop2: nor G2 (qn,s, q);
08:41 PM rue_shop2: endmodule
08:41 PM rue_shop2: that, and the outputs were backwards, which shouldn't ahve been able to happen
08:41 PM Tom_L: i may have mentioned that earlier, i foreget
08:41 PM rue_shop2: you did
08:41 PM rue_shop2: I presumed it was at the io level tho
08:41 PM rue_shop2: its not...
08:42 PM Tom_L: hmm
08:43 PM rue_shop2: that is really gonna mess me up
08:44 PM Tom_L: sry
08:44 PM Tom_L: :)
08:45 PM rue_shop2: it means an and is true when both its inputs are low
08:45 PM rue_shop2: how could they screw this up?
08:47 PM rue_shop2: but
08:47 PM rue_shop2: it must be soemthing that the logic gates are subject to, and not the higher level stuff
08:49 PM rue_shop2: ok, but reset works...
08:50 PM rue_shop2: whaaaaaat
08:53 PM rue_shop2: I wonder if all the problems I had with it counting down last night were from this
08:56 PM Tom_L: very likely
08:57 PM Tom_L: or at least it didn't help any
08:57 PM rue_shop2: I dont really know where the inversion is comming from
08:58 PM rue_shop2: set and reset work
08:58 PM rue_shop2: but the
08:58 PM rue_shop2: but
08:59 PM rue_shop2: its perfect counting down
08:59 PM rue_shop2: its just that it should be going up
09:00 PM rue_shop2: if its backwards at the DECODER
09:00 PM rue_shop2: and honestly, I think I did have problems right out of the gate with backwardsness
09:02 PM rue_shop2: my buddy wants help with his electrical and I have the sneaking suspicion he screwed up what I told him to prep
09:02 PM Tom_L: what's he want done?
09:02 PM rue_shop2: I really hope he didn't cut a full size hole for a vapor box in his cieling
09:02 PM rue_shop2: dunno, I'm going to just presume it all went ok and see
09:02 PM rue_shop2: somewhere around 8pm
09:02 PM rue_shop2: cause he works shift and we dont line up
09:03 PM Tom_L: ahh
09:03 PM Tom_L: i'm gettin used to that
09:03 PM Tom_L: my kids work odd shifts
09:03 PM Tom_L: and they just changed them due to the 737 grounding
09:04 PM rue_shop2: ?
09:04 PM rue_shop2: did someone ground all the 737?
09:05 PM Tom_L: FAA
09:05 PM rue_shop2: there couldn't have been a flaw found in the 737 _NOW_
09:05 PM Tom_L: they are scrambling to fix it
09:05 PM rue_shop2: its been like 40 years?
09:05 PM Tom_L: uh huh
09:05 PM Tom_L: it may have been later ones but i think they're all affected
09:05 PM rue_shop2: what about the other huge boing plane that are all grounded
09:06 PM Tom_L: i haven't followed exactly what the problem is
09:06 PM Tom_L: which one?
09:06 PM rue_shop2: the huge new one they screwed up the balance on cause of the engines
09:06 PM Tom_L: i dunno about that one
09:06 PM rue_shop2: their latest plane
09:07 PM rue_shop2: which are new, and all still grounded cause nobody can fix its problems via software?
09:08 PM rue_shop2: wait is 737MAX their new one?
09:09 PM Tom_L: i think so
09:09 PM Tom_L: likely the one with the software problem
09:09 PM rue_shop2: they been grounded almost since they were made
09:09 PM Tom_L: see, the client's didn't want to re'train their pilots
09:09 PM rue_shop2: they been sitting for months now
09:09 PM Tom_L: and the mods weren't added to the flight manual
09:10 PM Tom_L: so they didn't know what to do
09:11 PM rue_shop2: they put larger engines on them and they didn't fit so they moved them, and because the plane had a tendency to pitch up, they had the software pitch it down, but they messed it up and it threw a few into the ground
09:11 PM rue_shop2: https://en.wikipedia.org/wiki/Boeing_737_MAX_groundings
09:11 PM rue_shop2: that sounds like it alright
09:12 PM rue_shop2: there still isn't a fix iirc
09:12 PM Tom_L: not yet
09:12 PM rue_shop2: its probably the end of boeing
09:12 PM Tom_L: but that has trickled down to the machine shops and they're cutting hours
09:12 PM Tom_L: no
09:12 PM Tom_L: boeing will survive just fine
09:13 PM rue_shop2: yea, you sell that many planes that cant fly and dont fix it for over 6 months?
09:13 PM Tom_L: it's not their only pony in the stable
09:13 PM rue_shop2: how much are the planes, 13M?
09:13 PM rue_shop2: 2M?
09:14 PM Tom_L: i've no idea
09:14 PM rue_shop2: its been 8 months according to this...
09:15 PM Tom_L: i was talking to a former employee who seemed to know and they keep at least 3billion in cash on hand for things like this
09:15 PM rue_shop2: right, to give everyone two bought one a refund and scrap them all
09:15 PM rue_shop2: ?
09:15 PM Tom_L: they will fix it, it takes time to get things re certified
09:16 PM rue_shop2: ok, well the market is stupid, cause after the grounding they ahve sold another 50 of them
09:16 PM Tom_L: The company has suspended production of the 737 Max and the airliner remains grounded around the world, with no clear timetable on when it will fly again. ... Boeing says it has completed the necessary changes to repair the plane, but has said it won't carry passengers again until at least mid-2020.
09:16 PM rue_shop2: 6 billion $
09:17 PM rue_shop2: how much do ya think it costs/day to have a plane like that sit on the ground?
09:17 PM rue_shop2: I bet they dont hold heat well
09:17 PM Tom_L: https://www.boeing.com/737-max-updates/
09:19 PM Tom_L: i personally wouldn't fly anywhere right now
09:19 PM Tom_L: with the china virus going around
09:19 PM rue_shop2: I wanted to go to china sometime too :(
09:19 PM Tom_L: well, don't!
09:19 PM rue_shop2: I wonder if there will be a manufactiring hit
09:20 PM rue_shop2: my fallback is a trip across the states
09:20 PM Tom_L: and they're not known to be that truithful anyway
09:20 PM rue_shop2: visit you lot
09:20 PM rue_shop2: awefull spread out tho
09:20 PM Tom_L: yeah
09:20 PM rue_shop2: glad I didn't try it in my truck with those timing gears
09:20 PM rue_shop2: that would suck
09:21 PM rue_shop2: tho, probably wouldn't have cost as much to get fixed
09:22 PM rue_shop2: wtf, grrrr
09:22 PM Tom_L: they didn't offer any compensation? just re repaired it?
09:23 PM rue_shop2: I'v not grilled them on the price, but it sounds like I shouldn't bother
09:24 PM rue_shop2: wow, almost 8 hours of continiously waiting for fpga stuff to compile
09:24 PM rue_shop2: er 4
09:25 PM Tom_itx: NET "EINT" LOC = "P35" | IOSTANDARD = LVTTL | PULLUP; # Bank2 L48P_D7
09:26 PM Tom_L: just one i pulled from one of his pin files
09:30 PM Tom_itx: NET "LEDS<3>" LOC = "P6" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L33N_M3DQ13
09:30 PM Tom_itx: NET "OPTS<0>" LOC = "P79" | IOSTANDARD = LVTTL | PULLUP;
09:30 PM Tom_L: just a couple more for examples
09:33 PM rue_mohr: wait I think I'm a twitt
09:33 PM rue_mohr: I thnk the outputs need to come off the inverted outputs
09:45 PM rue_shop2: oooh
09:45 PM rue_shop2: ooops