#garfield Logs

Jan 29 2020

03:55 AM polprog: oh yeah, its snowing!
07:27 PM rue_mohr: how was the snow?
07:43 PM rue_mohr: ok, I'm alive, resetting my brain
07:57 PM rue_shop2: ok, fpga
08:06 PM rue_shop2: q <= 0; cannot assign to memory directly
08:06 PM rue_shop2: thats a clue
08:21 PM Tom_L: wrap in between begin and end
08:22 PM rue_shop2: I'm over it.. onto other issues
08:22 PM Tom_L: i haven't found all the possible errors yet :)
08:23 PM Tom_L: a good percent though
08:24 PM rue_shop2: I'm still tripping over basics
08:24 PM Tom_L: u n me both
08:28 PM Tom_L: i was looking over the quadrature code in the mesa cards
08:28 PM Tom_L: it's quite an elaborate piece of code
08:28 PM Tom_L: can do several different modes etc
08:30 PM rue_shop2: ERROR:HDLCompiler:1401 - "/files/programming/fpga/xilinx/spartin6/7seg_pt1/main.v" Line 32: Signal q[3] in unit decadeCounter is connected to following multiple drivers:
08:30 PM rue_shop2: I like that, thats where the error stops
08:31 PM Tom_L: are you using q[3] in 2 different spots?
08:31 PM Tom_L: it's when you try to assign it 2 values
08:31 PM rue_shop2: I have to places I assign q and that doesn't work
08:31 PM Tom_L: that's what the error is
08:31 PM rue_shop2: yep
08:39 PM rue_shop2: oh damn, its smart
08:40 PM rue_shop2: it didn't build the clock system cause I didn't make code what would change with it
08:51 PM Tom_L: :)
09:07 PM rue_shop2: ok, I got a digit counting form 0-9
09:07 PM rue_shop2: adding a carry flag
09:09 PM rue_shop2: https://paste.debian.net/1128287/
09:09 PM rue_shop2: I dont like that the decoder uses a register for the output, but I cant do anything about it
09:10 PM rue_shop2: it doens't look like it uses an actual register in the implementation so..
09:11 PM rue_shop2: oops, that didn't work
09:13 PM rue_shop2: I goofed it when I added the carry
09:13 PM rue_shop2: Tom_L, you alive tonight?
09:15 PM rue_shop2: ok, got it
09:15 PM rue_shop2: 4'h0 : {q, c} <= {4'd1, 1'b0}; //'0'
09:15 PM rue_shop2: numbers are 32 bit unless you specify
09:17 PM rue_shop2: ok, testing carry without a multiplexor
09:17 PM rue_shop2: decadeCounter U2 (clkdown[22], 0, bus1, c1);
09:17 PM rue_shop2: decadeCounter U3 (c1, 0, bus2, c2);
09:19 PM rue_shop2: yes, its happy
09:20 PM rue_shop2: I wonder how you specify no connection
09:27 PM rue_shop2: hmm intersting new syntax...
09:28 PM rue_shop2: testing...
09:29 PM rue_shop2: ok, that didn't work
09:40 PM rue_shop2: I thought I was on to a syntax that would let me drop the wires
09:49 PM rue_shop2: No support for synthesis of mixed edge and level triggers.
09:49 PM rue_shop2: hmmm
09:53 PM rue_shop2: Assignment under multiple single edges is not supported for synthesis
09:55 PM Tom_L: bak for a bit
09:55 PM rue_shop2: I'm not sure how to do the asynchronous reset of the counter
09:56 PM Tom_L: with a button you mean?
09:56 PM rue_shop2: no, the counter is set up as a state machie that steps on a clock edge
09:56 PM Tom_L: oh
09:56 PM rue_shop2: but I want the reset signal to zero it whenever it is hich
09:56 PM rue_shop2: high
09:56 PM rue_shop2: and thats a conflict
09:56 PM rue_shop2: I have a synchronous reset working
09:57 PM Tom_L: you can't use the main clock and test for conditions?
09:57 PM rue_shop2: trying to do this as if its a chip
09:57 PM Tom_L: you can't
09:57 PM rue_shop2: module decadeCounter( input clk, input rst, output reg[3:0] q, output reg c );
09:57 PM rue_shop2: not sold yet
09:58 PM Tom_L: the main clock makes everything happen at the same time
09:58 PM rue_shop2: I think I can and I'm not being clever enough
09:58 PM Tom_L: it's not one nice stream of code
09:58 PM rue_shop2: yes, but thats not what I'm on about
09:58 PM Tom_L: i know
09:58 PM Tom_L: but that was biting me too
09:58 PM rue_shop2: I want the counter to count if it gets a clock edge
09:58 PM rue_shop2: and be zero if its under reset
09:59 PM rue_shop2: I cant have multiple things modify the value register
09:59 PM Tom_L: can you xor something to get it?
09:59 PM rue_shop2: yea, I'm thinkin
09:59 PM Tom_L: bak in a few
10:07 PM Tom_L: ok
10:10 PM Tom_L: i don't get the 2nd part of that post
10:15 PM rue_shop2: I'm all over the map
10:15 PM rue_shop2: I found a new way to do the 7 seg decoder that doesn't use registers
10:18 PM rue_shop2: YES
10:24 PM rue_shop2: huh, I dont know if its more efficient
10:26 PM Tom_L: that post seems to be the way most are done
10:26 PM Tom_L: with different flavors added here and there
10:27 PM rue_shop2: this is currently me code...
10:27 PM rue_shop2: https://paste.debian.net/1128293/
10:28 PM rue_shop2: just making a johnson counter for strobing the displays
10:28 PM Tom_L: close the ) on clock
10:28 PM Tom_L: 54
10:28 PM rue_shop2: I'm just writing it
10:28 PM Tom_L: i know
10:28 PM rue_shop2: always @ (posedge clk)
10:28 PM rue_shop2: if (!rst)
10:28 PM rue_shop2: begin
10:28 PM rue_shop2:
10:28 PM rue_shop2: end
10:28 PM rue_shop2: else
10:29 PM rue_shop2: literally writing it now
10:31 PM rue_shop2: I need to work out reset
10:31 PM rue_shop2: I should be able to make a 10 bit johnson counter and feed the rest back from an output where I want to reset it
10:32 PM Tom_L: you like playing with state code
10:32 PM rue_shop2: :)
10:32 PM Tom_L: gives you an open field to do it
10:33 PM rue_shop2: your genious
10:33 PM rue_shop2: if I cant modify the output, I modify the input
10:33 PM rue_shop2: I wonder
10:34 PM rue_shop2: bah I dont know how to write it
10:34 PM Tom_L: where you at on it?
10:34 PM Tom_L: what lines
10:34 PM rue_shop2: decadecounter has a latch
10:34 PM rue_shop2: the clock of the latch is the clk input
10:35 PM rue_shop2: but both sides of the latch are reffered to as d
10:35 PM rue_shop2: er
10:35 PM rue_shop2: q
10:35 PM rue_shop2: so, to reset, I cant re-direct the input of the table from the latch to a static value
10:35 PM rue_shop2: but even if I could, its still latched
10:35 PM rue_shop2: hmmmm
10:36 PM Tom_L: what value would q be on reset?
10:36 PM rue_shop2: 0
10:36 PM rue_shop2: but I cant make q count on an edge AND be 0 when rst is high
10:36 PM Tom_L: so is q a register?
10:37 PM rue_shop2: yes
10:37 PM Tom_L: so tell it that it is
10:37 PM rue_shop2: no
10:37 PM Tom_L: you did
10:37 PM rue_shop2: you cant have an edge AND a level control a register
10:37 PM Tom_L: in 59
10:38 PM rue_shop2: but I cant have the level of rst control q
10:39 PM Tom_L: what else sets q?
10:39 PM Tom_L: q is an input
10:39 PM rue_shop2: that whole case statement below it
10:39 PM rue_shop2: output reg[3:0] q
10:39 PM Tom_L: no q is an ouput i see that now
10:39 PM Tom_L: i like to list them below the function declaration
10:40 PM rue_shop2: what I want is a D latch with a data, clock, preset, and reset, what I have is a d latch with a data and clock
10:40 PM rue_shop2: I'm playing with the two, flipflopping a bit
10:41 PM Tom_L: https://www.xilinx.com/support/documentation/university/ISE-Teaching/HDL-Design/14x/Nexys3/Verilog/docs-pdf/lab5.pdf
10:43 PM rue_shop2: oh its a pdf
10:43 PM Tom_L: https://www.fpga4student.com/2017/02/verilog-code-for-d-flip-flop.html
10:44 PM rue_shop2: no I do not want to build my own data latch from flipflops
10:44 PM rue_shop2: however there may be a clue
10:45 PM Tom_L: i read alot of code
10:45 PM Tom_L: cause i haven't found any really good tutorials
10:46 PM rue_shop2: no they skip over it
10:46 PM Tom_L: i was trying to code both verilog and vhdl but that wasn't working out
10:46 PM rue_shop2: oh, at the end they say it exists
10:47 PM rue_shop2: D Flip-Flop with Asynchronous Clear and Clock Enable
10:47 PM Tom_L: i figured there might be one...
10:49 PM rue_shop2: wait
10:49 PM rue_shop2: always @(posedge Clk or posedge clear)
10:49 PM rue_shop2: when I tried this it said no
10:50 PM rue_shop2: Line 97: Assignment under multiple single edges is not supported for synthesis
10:53 PM Tom_L: looking at one of my examples they did it
10:53 PM rue_shop2: will it compile?
10:53 PM Tom_itx: module Counter_M10 ( clk, reset, q, cout );
10:53 PM Tom_itx: always @( posedge clk or posedge reset )
10:53 PM rue_shop2: wtf
10:54 PM Tom_L: those are both input wires
10:54 PM rue_shop2: module decadeCounter( input clk, input rst, output reg[3:0] q, output reg c );
10:54 PM rue_shop2:
10:54 PM rue_shop2:
10:54 PM rue_shop2:
10:54 PM rue_shop2: always @ (posedge clk or posedge rst)
10:54 PM rue_shop2: if (!rst)
10:54 PM rue_shop2: I'm doing like exactly the same thing
10:54 PM Tom_itx: input wire clk;
10:54 PM Tom_itx: input wire reset;
10:54 PM rue_shop2: trying
10:55 PM Tom_itx: begin
10:55 PM Tom_itx: if( reset )
10:56 PM rue_shop2: wait a min...
10:57 PM Tom_L: i would personally put the labels in the function header and define what they are below it
10:58 PM Tom_L: listing the inputs first
10:58 PM rue_shop2: wait, I think it didn't like the !
10:58 PM Tom_L: yeah i was trying to find a reference about that
10:58 PM rue_shop2: why wouldn't it?
10:58 PM rue_shop2: ok, hold on, its working...
10:58 PM rue_shop2: waiting to recompile...
10:59 PM rue_shop2: always @ (posedge clk or posedge rst)
10:59 PM rue_shop2: if (rst)
10:59 PM rue_shop2: begin
10:59 PM rue_shop2: {q, c} <= {4'd0, 1'b0};
10:59 PM rue_shop2: end else
10:59 PM rue_shop2: begin
10:59 PM rue_shop2: just swapped the blocks without the rst inversion
10:59 PM Tom_L: :)
10:59 PM rue_shop2: hu!?
10:59 PM Tom_L: i had to do that somewhere because i couldn't figure it out
11:00 PM Tom_L: ! is unary
11:00 PM rue_shop2: sire
11:00 PM rue_shop2: and rst is 1 bit
11:00 PM Tom_L: !== is equality
11:00 PM rue_shop2: ~ is otherwise invert
11:00 PM Tom_L: yes
11:00 PM rue_shop2: see if this works first, stand by
11:01 PM Tom_itx: http://www.verilog.renerta.com/source/vrg00031.htm
11:01 PM rue_shop2: you see how I get a carry tho eh?
11:01 PM rue_shop2: it working to feed that into the clock of another instance
11:02 PM rue_shop2: yea it works
11:02 PM rue_shop2: good call
11:02 PM rue_shop2: trying ~ for the hell of it
11:03 PM Tom_L: trying to remember when to use what gets confusing
11:03 PM rue_shop2: C doesn't care depending
11:03 PM Tom_L: this ain't your average C
11:03 PM rue_shop2: well, no, and its not giving any leeway
11:03 PM rue_shop2: yea, its find with ~
11:03 PM rue_shop2: huh
11:04 PM rue_shop2: so, I wonder if I can wrap the reset of the johnson counter
11:05 PM rue_shop2: ok, I have 3 4 bit decade counters
11:05 PM rue_shop2: I have a 7 segment decoder
11:06 PM rue_shop2: I have a 3 bit johnson counter
11:06 PM rue_shop2: so I need a data bus selector
11:06 PM * Tom_L gives rue_shop2 a bottle of glue
11:07 PM rue_shop2: andwire[0:3] encoderbus
11:07 PM rue_shop2: maybe
11:07 PM Tom_L: you want that backwards?
11:08 PM rue_shop2: you have have wires do AND and OR functions
11:08 PM rue_shop2: there is also a tristate thing
11:10 PM Tom_L: was that guy any help with your motor driver?
11:11 PM rue_shop2: he's using a chip that wont work for me
11:11 PM rue_shop2: its horrid anyhow
11:11 PM rue_shop2: dumps like 26w at 8A
11:15 PM rue_shop2: seg7Decoder U1 ((digSel == 3'001)?bus1:(digSel == 3'010)?bus2:(digSel == 3'100)?bus3, {U8_47, U8_49, U8_51, U8_53, U8_55, U8_57, U8_59});
11:15 PM rue_shop2: this line is getting long
11:16 PM Tom_L: you shouldn't need the == there, = should work
11:18 PM rue_shop2: you know
11:18 PM rue_shop2: I'm gonna slip, blow this up, and be sad
11:20 PM Tom_L: or it will just work
11:24 PM rue_shop2: I stuffed in 3 transistors, 2N7000, cause they dont need resistors
11:24 PM rue_shop2: compiling what SHOULD strobe thru them
11:24 PM rue_shop2: then I'm out of time tonight
11:24 PM Tom_L: for the anodes?
11:24 PM rue_shop2: cc
11:24 PM Tom_L: i'm wrapping it up myself
11:25 PM rue_shop2: so, you see how I did my code anyhow
11:25 PM Tom_L: somewhat
11:25 PM rue_shop2: and I used wires to intertie everything
11:26 PM rue_shop2: huh, didn't work
11:26 PM Tom_L: more efficient?
11:26 PM Tom_L: did you add all the pins to the pin file?
11:26 PM rue_shop2: dunno
11:27 PM rue_shop2: its there, something didn't do right
11:27 PM Tom_L: i've forgotten that before and nothing happens
11:27 PM rue_shop2: I need to init the johnston counter
11:27 PM rue_shop2: whats default on a case?
11:27 PM Tom_L: whatever you make it
11:28 PM rue_shop2: no syntax
11:28 PM Tom_L: default : xxx = yyy;
11:28 PM Tom_L: just replace it with the input data
11:29 PM rue_shop2: my johnson counter is inherrintly unstable
11:29 PM rue_shop2: any illegal value and it just stops
11:29 PM rue_shop2: :)
11:29 PM rue_shop2: powerup is an illegal value
11:29 PM rue_shop2: :)
11:30 PM Tom_L: i'm goin to bed
11:30 PM rue_shop2: 1 compile to know if my strobing works
11:31 PM rue_shop2: yes, but I got the scan freq really wrong
11:31 PM rue_shop2: and the digits backwards :)
11:31 PM Tom_L: i think i mentioned that
11:31 PM Tom_L: err no that was something else
11:31 PM rue_shop2: :) recompiling, gnight
11:34 PM Tom_L: you have to have a default on a case btw
11:37 PM rue_shop2: na
11:38 PM rue_shop2: got it tho
11:38 PM rue_shop2: did you see that other video?
11:38 PM rue_shop2: from twit?
11:39 PM rue_shop2: https://paste.debian.net/1128299/
11:39 PM rue_shop2: tonights closing code
11:41 PM Tom_L: missed the video
11:55 PM rue_mohr: https://twitter.com/RueNahcMohr/status/1222757374374469632
11:55 PM rue_mohr: I did one other thing to slow it down a bit, but yea
11:56 PM rue_mohr: https://twitter.com/RueNahcMohr/status/1222406869399945216 <-- that was the one last night