#garfield Logs
Jan 02 2020
#garfield Calendar
01:30 AM rue_: arg
01:41 AM rue_ is now known as rue_mohr
01:29 PM Tom_L: http://tom-itx.no-ip.biz:81/~webpage/temp/xilinx/dpll_ref_design/
07:05 PM rue_mohr: did you do one up or was it already done?
07:32 PM rue_shop1: so, the timing gear story gets deeper
07:32 PM rue_shop1: I got a set of gears from our other auto supplier here
07:33 PM rue_shop1: turns out, exact same box as what GM gave me my old gears back
07:33 PM rue_shop1: and, the gears I got are a perfect size match to the orig
07:33 PM rue_shop1: the suspicion is that they put them on backwards
07:44 PM rue_shop3: http://www.verilog.renerta.com/source/vrg00010.htm
07:44 PM rue_shop3: this seems like a good site
08:12 PM Tom_L: no that's their reference files
08:12 PM Tom_L: they suggest using them as a starting point for projects
08:13 PM Tom_L: i wondered if they might have put them on backwards but the timing mark wouldn't be there if they did
08:53 PM rue_shop3: yea
08:53 PM rue_shop3: funny thing
08:53 PM rue_shop3: when I asked if the gears were aligned
08:53 PM rue_shop3: they said yes like they had a HELL of a time with it
08:54 PM rue_shop3: primitive test(O, I);
08:54 PM rue_shop3: ...
08:57 PM rue_shop3: do you understand delay values yet?
08:57 PM Tom_L: gear alignment isn't that difficult
08:57 PM rue_shop3: #10
08:57 PM rue_shop3: ?
08:57 PM Tom_L: no
08:57 PM rue_shop3: it is if they are on backwards
08:57 PM rue_shop3: aka, dots against engine
08:58 PM Tom_L: i haven't seen the gears so dunno if that's possible
08:58 PM Tom_L: i'm sure any idiot could do it wrong though
08:58 PM rue_shop3: yea
08:58 PM rue_shop3: you have to press it on too
08:58 PM rue_shop3: you cant just take it off and turn it around
08:58 PM rue_shop3: the old gear dies
08:58 PM Tom_L: i'm wondering how they pressed it in the engine
08:59 PM rue_shop3: there is a posulation that the cam shaft has a threaded hole
08:59 PM rue_shop3: aka, use a bolt to push it on
08:59 PM Tom_L: it might but it's supposed to be done out of the engine
08:59 PM rue_shop3: yup
09:00 PM Tom_L: it may have a centering dimple instead of a threaded hole too
09:00 PM Tom_L: for grinding
09:00 PM rue_shop3: yea
09:01 PM Tom_L: i read about delay but don't remember much
09:03 PM Tom_itx: Delay Control (#)
09:03 PM Tom_itx: A delay control expression specifies the time duration between initially encountering the
09:03 PM Tom_itx: statement and when the statement actually executes. For example:
09:04 PM Tom_itx: #10 A = A + 1;
09:04 PM Tom_itx: specifies to delay 10 time units before executing the procedural assignment statement. The # may
09:04 PM Tom_itx: be followed by an expression with variables.
09:04 PM rue_shop3: ah, this is to deal with the fact that everything happens at the same time
09:05 PM rue_shop3: my pwm, I had to do the counter increment on the rising edge, and the compare on the falling
09:05 PM rue_shop3: they were happening at the wrong times and the compare wan't catching
09:05 PM rue_shop3: er, kinda
09:05 PM rue_shop3: sorry, half asleep
09:05 PM rue_shop3: I did a counter that goes from 0-31 and back to 0
09:06 PM rue_shop3: it wasn't catching the 0 and 31 properly cause the ops were in the wrong order
09:06 PM Tom_L: http://tom-itx.no-ip.biz:81/~webpage/xilinx/New_Board/EX2-PWM_LED/PWM_LED.v
09:06 PM rue_shop3: (so I used rising vs falling edge)
09:06 PM Tom_L: that's my board's pwm example
09:07 PM rue_shop3: always @ (posedge clkdown[18]) begin
09:07 PM rue_shop3: if (count == 0) begin
09:07 PM rue_shop3: dir <= 1;
09:07 PM rue_shop3: end
09:07 PM rue_shop3:
09:07 PM rue_shop3: if (count == 6'b111111) begin
09:07 PM rue_shop3: dir <= 0;
09:07 PM rue_shop3: end
09:07 PM rue_shop3: end
09:07 PM rue_shop3:
09:07 PM rue_shop3: always @ (negedge clkdown[18]) begin
09:07 PM rue_shop3: if (dir == 1) count <= count + 1'b1;
09:07 PM rue_shop3: else count <= count - 1'b1;
09:07 PM rue_shop3: end
09:07 PM rue_shop3: ugh
09:07 PM rue_shop3: https://paste.debian.net/1124267/
09:07 PM rue_shop3: :)
09:07 PM Tom_L: hah
09:07 PM rue_shop3: see what I mean tho eh?
09:08 PM Tom_L: yeah
09:08 PM rue_shop3: ooo my primitive worked!
09:08 PM Tom_L: i've not seen negedge used yet
09:08 PM rue_shop3: I was kinda guessing too :)
09:08 PM Tom_L: what is a primitive for?
09:09 PM Tom_L: is it kindof like a function declaration before the function in a .c .h file set?
09:09 PM rue_shop3: https://paste.debian.net/1124268/
09:09 PM rue_shop3: I think I can use it for lookup tables that dont need to be loaded into memory
09:09 PM rue_shop3: but I ... need to play more...
09:10 PM rue_shop3: so
09:10 PM rue_shop3: if I want a value to be more than 1 bit
09:10 PM rue_shop3: primitive test(O, I);
09:11 PM rue_shop3: I need to put the [] in there or below
09:11 PM rue_shop3: primitive test(O[1:0], I[1:0]); ?
09:11 PM rue_shop3: and / or output O[1:0]
09:11 PM rue_shop3: there are two methods going around and they mixed me up
09:12 PM Tom_L: doesn't look right but i dunno
09:12 PM rue_shop3: well, in a module
09:12 PM rue_shop3: if you have more than one bit on a ... argument, how do ya write it?
09:13 PM Tom_L: hang on
09:14 PM rue_shop3: https://personal.utdallas.edu/~jxw143630/index_files/Page5212.htm
09:14 PM rue_shop3: I think the input and output lines...
09:15 PM Tom_L: you declare it in the module header then define it below that
09:15 PM rue_shop3: k
09:16 PM Tom_L: module Arithmetic (A, B, Y1, Y2, Y3, Y4, Y5);
09:16 PM Tom_L: input [2:0] A, B;
09:16 PM Tom_L: output [3:0] Y1;
09:16 PM Tom_L: output [4:0] Y3;
09:16 PM rue_shop3: yea
09:16 PM Tom_L: outputs are 4 & 5 element
09:16 PM Tom_L: then if you want a bit from it....
09:16 PM rue_shop3: heh, I got the order backwards and it barfed, thanks for re-echoing
09:17 PM Tom_L: i don't remember :)
09:17 PM rue_shop3: input [1:0] I;
09:17 PM Tom_L: maybe output[3] output[2]
09:17 PM Tom_L: for bits
09:17 PM rue_shop3: loosk right? it doesn't like it
09:18 PM Tom_L: input[1:0], I,J;
09:18 PM Tom_L: there are 2
09:18 PM Tom_L: ?
09:19 PM rue_shop3: hmm, it doens't like me trying to do this
09:19 PM rue_shop3: primitive test(O, I);
09:19 PM rue_shop3: output O;
09:19 PM rue_shop3: input[1:0] I;
09:19 PM rue_shop3: ?
09:19 PM Tom_L: figuring out the syntax takes some doing
09:19 PM Tom_L: once you do then switch to vhdl and start all over
09:20 PM Tom_L: input[1:0] would be input(1 downto 0) in vhdl
09:20 PM Tom_L: or upto if it's reversedd
09:21 PM rue_shop3: it looks like you cant squash multibit arrays into primitives
09:21 PM Tom_L: i haven't gotten into primitives yet
09:22 PM Tom_L: actually vhdl would be: in std_logic_vector(1 downto 0)
09:22 PM Tom_L: ;
09:23 PM Tom_L: a single bit would be in std_logic;
09:23 PM Tom_L: a single bit would be x : in std_logic;
09:28 PM rue_shop3: primitives can only take 1 bit values
09:28 PM rue_shop3: so I cant do what I want in a way thats worth doing it
09:32 PM rue_shop3: I can come closer with module and case
09:32 PM rue_shop3: er not
09:33 PM Tom_L: udp primitives
09:33 PM Tom_itx: http://www.asic-world.com/verilog/udp1.html
09:34 PM Tom_itx: <table_definition>
09:34 PM Tom_itx: ::= table
09:34 PM Tom_itx: <table_entries>
09:34 PM Tom_itx: endtable
09:34 PM rue_shop3: yes, the values in the table have to be 1 bit
09:34 PM Tom_L: hmm
09:34 PM rue_shop3: arg, case isn't working for me either
09:35 PM rue_shop3: https://paste.debian.net/1124272/
09:35 PM rue_shop3: can you fix? I'm working on it
09:35 PM Tom_itx: case(cnt)
09:35 PM Tom_itx: / D is bcd for the 4 display segments 16bit for up count
09:35 PM Tom_itx: 3'b001: begin Muxout = D[3:0]; an [3:0] = 4'b1000; end
09:35 PM Tom_itx: 3'b010: begin Muxout = D[7:4]; an [3:0] = 4'b0100; end
09:35 PM Tom_itx: 3'b011: begin Muxout = D[11:8]; an [3:0] = 4'b0010; end
09:35 PM Tom_itx: 3'b100: begin Muxout = D[15:12]; an [3:0] = 4'b0001; cnt [2:0] = 3'b000; end
09:35 PM Tom_itx: endcase
09:35 PM Tom_L: one i did
09:36 PM rue_shop3: was cnt a register?
09:36 PM Tom_L: begin.... end each case statement
09:36 PM Tom_L: a counter
09:36 PM Tom_itx: cnt = cnt+1;
09:36 PM rue_shop3: reg
09:36 PM rue_shop3: ?
09:36 PM rue_shop3: reg cnt?
09:37 PM Tom_itx: reg [2:0] cnt;
09:37 PM Tom_itx: yes
09:37 PM Tom_itx: module top(q,mux,cnt......
09:38 PM rue_shop3: yea everyone uses regs for everything,
09:38 PM rue_shop3: its bugin me
09:39 PM Tom_L: i'm learning by examples
09:39 PM Tom_L: may be bad examples...
09:39 PM Tom_L: you did clear something up for me just now though
09:39 PM Tom_L: :)
09:39 PM Tom_L: i think
09:40 PM Tom_L: a use of # i couldn't figure out
09:41 PM Tom_itx: reg is like declaring a variable in c etc
09:41 PM rue_shop3: :) as we both trample all over things :)
09:41 PM rue_shop3: yes, but its a latched value
09:42 PM Tom_itx: clkdiv #(23) u1(clk, q);
09:42 PM rue_shop3: aka, a clock has to happen before its valid
09:42 PM Tom_itx: doesn't that wait 23 cycles then asign the value?
09:42 PM rue_shop3: maybe :)
09:42 PM rue_shop3: (dunno)
09:42 PM Tom_itx: so it works as a clock divider
09:42 PM rue_shop3: k
09:42 PM Tom_itx: i know it's a divider just didn't know how
09:42 PM rue_shop3: I wonder how its implmentation is different than a counter
09:43 PM Tom_itx: ^^ that's not complete
09:43 PM Tom_itx: it calls a clock divider function i think
09:44 PM rue_shop3: whcih might use the same number of flipflops (??)
09:44 PM Tom_L: that one is the delay time between counts on my hex counter
09:45 PM Tom_itx: module clkdiv(clk,q); // Oscillator is 25.175 Mhz
09:45 PM Tom_itx: input clk;
09:45 PM Tom_itx: output q;
09:45 PM Tom_itx: parameter BITS=24; // 20
09:45 PM Tom_itx: reg [23:0] COUNT; // 19
09:45 PM Tom_itx: initial COUNT=0;
09:45 PM Tom_itx: assign q=COUNT[BITS-1]; // parameterize the counter
09:45 PM Tom_itx: always @(posedge clk)
09:45 PM Tom_itx: begin
09:45 PM Tom_itx: COUNT = COUNT + 1;
09:45 PM Tom_itx: end
09:45 PM Tom_itx: endmodule
09:45 PM rue_shop3: tom I cant make a case work
09:45 PM Tom_L: yes you can
09:47 PM rue_shop3: https://paste.debian.net/1124274/
09:47 PM Tom_itx: https://paste.debian.net/1124275/
09:48 PM rue_shop3: I think your ends are vhdl, but Ill try
09:48 PM Tom_itx: with I = I+1; just above the case statement
09:49 PM rue_shop3: ERROR:HDLCompiler:806 - "/files/programming/fpga/xilinx/spartin6/stateMachine/blink.v" Line 38: Syntax error near "end".
09:49 PM Tom_itx: or just assign it a value
09:49 PM Tom_itx: post it
09:50 PM rue_shop3: https://paste.debian.net/1124276/
09:51 PM Tom_itx: https://paste.debian.net/1124275/
09:51 PM rue_shop3: end must be vhdl
09:51 PM Tom_itx: O: begin
09:51 PM Tom_itx: no
09:51 PM rue_shop3: on you need begin and end!
09:51 PM rue_shop3: ???
09:51 PM rue_shop3: ugh
09:51 PM Tom_itx: / case v_CONCATENATE is
09:51 PM Tom_itx: / when "000" | "100" =>
09:51 PM Tom_itx: / r_RESULT <= 0;
09:51 PM Tom_itx: / when "001" =>
09:51 PM Tom_itx: / r_RESULT <= 1;
09:51 PM Tom_itx: that's vhdl :(
09:51 PM Tom_itx: )
09:52 PM rue_shop3: why dont we add 500 characters of other garbage in there for no reason...
09:52 PM rue_shop3: trying...
09:52 PM Tom_itx: you don't need assign either
09:52 PM rue_shop3: I do if its not a register
09:52 PM Tom_itx: O: begin out = 1; end
09:53 PM Tom_itx: sry remove the ';' after end on the paste
09:53 PM Tom_itx: just habit
09:53 PM rue_shop3: trying thigns....
09:54 PM rue_shop3: ERROR:HDLCompiler:53 - "/files/programming/fpga/xilinx/spartin6/stateMachine/blink.v" Line 32: <I> is not a port.
09:54 PM rue_shop3: ERROR:HDLCompiler:44 - "/files/programming/fpga/xilinx/spartin6/stateMachine/blink.v" Line 36: I is not a constant
09:54 PM Tom_itx: reg eat more gates is that's what's buggin ya?
09:54 PM rue_shop3: its implying that the input value has to be static
09:54 PM rue_shop3: its like a stoplight at every intersection
09:54 PM rue_shop3: well, stopsign
09:54 PM Tom_itx: it's steep at the beginning but there is a top to the hill
09:54 PM rue_shop3: stop, even if there is no traffic
09:55 PM Tom_itx: i fought 'case' for 2 weeks
09:56 PM rue_shop3: https://www.nandland.com/verilog/examples/example-case-statement.html
09:56 PM rue_shop3: is what someone says
09:57 PM Tom_itx: yeah
09:57 PM Tom_itx: 3'b000 3 bit binary value 000
09:58 PM Tom_itx: i don't know enough to say that's right or wrong
09:58 PM Tom_itx: their example
09:58 PM rue_shop3: there is another example in a pdf...
09:58 PM Tom_itx: mine works
09:58 PM rue_shop3: https://www.csee.umbc.edu/~tinoosh/cmpe415/slides/Rom-LUT-verilog.pdf
09:58 PM rue_shop3: I'm missing the always
09:59 PM Tom_itx: yeah
09:59 PM Tom_itx: you need it inside a begin ... end statement
10:00 PM Tom_itx: always@(posedge clk)
10:00 PM Tom_itx: begin
10:00 PM Tom_itx: case
10:00 PM Tom_itx: 1
10:00 PM Tom_itx: 2
10:00 PM Tom_itx: 3
10:00 PM Tom_itx: 4
10:00 PM Tom_itx: endcase
10:00 PM Tom_itx: end
10:02 PM Tom_itx: always@(posedge clk) ... it needs to know when to do it
10:02 PM Tom_itx: could be in a slower loop or whatever
10:02 PM rue_shop3: oh, soemthing can be an output and a reg at the same time
10:02 PM Tom_itx: yes
10:02 PM Tom_itx: i define them as both
10:03 PM Tom_itx: output ld;
10:03 PM Tom_itx: reg ld;
10:03 PM Tom_itx: and put ld in the module xxx(ld)
10:03 PM rue_shop3: ok, so always @*
10:04 PM rue_shop3: opposed to a clock edge?
10:04 PM Tom_itx: you can try that, i'm not sure what * does
10:04 PM rue_shop3: ah it working
10:04 PM rue_shop3: * is anything I think
10:04 PM rue_shop3: posedge, negedge, and its friends
10:04 PM Tom_itx: * grabs any declaration you may have missed
10:04 PM rue_shop3: (??) :)
10:05 PM Tom_itx: oh so any edge
10:05 PM Tom_itx: or transistion
10:05 PM Tom_itx: so posedge will be half of *
10:05 PM rue_shop3: I think it can be called "not blocked" it just takes it when it gets it
10:05 PM Tom_itx: as will negedge
10:05 PM rue_shop3: aha
10:06 PM rue_shop3: https://paste.debian.net/1124278/
10:06 PM Tom_L: * any transition
10:07 PM Tom_itx: where did you get 'd' from?
10:07 PM Tom_itx: decimal?
10:07 PM rue_shop3: decimal
10:07 PM Tom_itx: decible
10:07 PM rue_shop3: I was getting verbose as it was being stupid
10:07 PM rue_shop3: test(U8_47, {count[4], count[5]});
10:08 PM Tom_itx: v and vhdl are more exacting than some
10:08 PM rue_shop3: output is U8_47 (the pin on my board) and the input is 2 bits composed of...
10:08 PM rue_shop3: actaully, I think I got the msb on the wrong side TECHNICALLY
10:09 PM Tom_itx: you make a .ucf file for your pins?
10:09 PM rue_shop3: yes
10:09 PM rue_shop3: NET "U8_41" Loc = P4 | IOSTANDARD = SDIO;
10:09 PM rue_shop3: NET "U8_43" Loc = P5 | IOSTANDARD = SDIO;
10:09 PM rue_shop3: NET "U8_45" Loc = M7 | IOSTANDARD = SDIO;
10:09 PM rue_shop3: ...
10:09 PM rue_shop3: I named them for where they are on the board
10:09 PM rue_shop3: so I can find them when wiring it
10:09 PM rue_shop3: I had one of the guys helping me on the vaccation
10:10 PM Tom_itx: does he know verilog?
10:10 PM rue_shop3: zhanx, where are you
10:10 PM rue_shop3: were playing with fpgas
10:10 PM rue_shop3: well, he did in uni, for a bit
10:10 PM rue_shop3: we were both lost tho
10:10 PM Tom_L: well i did 20 yrs ago a bit :)
10:10 PM rue_shop3: :)
10:11 PM Tom_L: but i found it fun
10:11 PM rue_shop3: yea, this isn't too bad
10:11 PM rue_shop3: nice to have somthing working to play on
10:11 PM Tom_L: i like seeing results
10:11 PM rue_shop3: annoying it takes 4 mintues to generate program file
10:11 PM Tom_L: heh
10:11 PM Tom_L: get a faster pc
10:11 PM Tom_L: it does take a bit
10:12 PM rue_shop3: ok that worked
10:12 PM Tom_L: oh
10:12 PM Tom_L: comments in the .v file are different than in the .ucf file
10:13 PM Tom_L: / is in the .v and # is in the .ucf
10:13 PM Tom_L: / is in the .v and # is in the .ucf for comment lines
10:13 PM rue_shop3: I dont mind sticking with verilog for now
10:13 PM Tom_L: "//" is in the .v and # is in the .ucf for comment lines
10:13 PM Tom_L: damn irc
10:13 PM rue_shop3: :) I knoew
10:14 PM Tom_L: i can go either way, doesn't matter
10:14 PM Tom_L: initially verilog will seem easier
10:16 PM rue_shop3: I'm pondering a P servo loop controller
10:16 PM rue_shop3: (not yet)
10:16 PM zhanx: here
10:16 PM Tom_L: self tuning?
10:16 PM Tom_L: of course
10:16 PM rue_shop3: hah
10:17 PM rue_shop3: fpgas are no longer on a pedistal with me
10:18 PM Tom_L: you need another port for something... just add one :)
10:18 PM rue_shop3: their just cpld's that lose their !@#!#$^% with powerdown
10:19 PM Tom_L: exactly
10:19 PM rue_shop3: sure, I was also pondering a 100 channel hobby servo controller
10:19 PM rue_shop3: using a huge shift register for input position control
10:19 PM Tom_L: that's why they have the flash chip on all the dev boards you see
10:19 PM rue_shop3: indeed
10:19 PM rue_shop3: haha, this looks like its going to work
10:19 PM rue_shop3: I'll wait and show ya
10:19 PM Tom_L: i'm wondering where mine will load code when i get it
10:20 PM Tom_L: or if i'll have to figure that out
10:20 PM rue_shop3: prolly has an onboard nand
10:20 PM rue_shop3: hahah this is working
10:20 PM rue_shop3: https://paste.debian.net/1124279/
10:21 PM Tom_itx: uh oh... he's having fun now
10:21 PM rue_shop3: didn't know if I could do this
10:21 PM rue_shop3: its almost generated
10:22 PM * rue_shop3 finishes the table...
10:23 PM rue_shop3: evil bit manipulation
10:23 PM rue_shop3: test(U8_47, {count[4], count[5]}, count[3]);
10:26 PM Tom_L: you still haven't used 1% of 1% of your gates
10:27 PM rue_shop3: I know
10:27 PM rue_shop3: actually, we were up to 0.15%
10:27 PM rue_shop3: we checked
10:27 PM rue_shop3: :)
10:29 PM rue_shop3: assign U8_45 = clkdown[5:0] > count[5:0] ? 0 : 1;
10:29 PM rue_shop3: there is my pwm by the way
10:29 PM rue_shop3: clkdown is my clock divider
10:29 PM rue_shop3: count is the pwm value
10:29 PM Tom_L: yeah
10:30 PM rue_shop3: it does, of couse, have glitches
10:30 PM rue_shop3: hmm
10:40 PM rue_shop3: https://paste.debian.net/1124281/
10:40 PM rue_shop3: so close
10:52 PM rue_shop1: wow my ass doesn't like this much sitting
10:53 PM Tom_L: i couldn't even focus on the screen last night
10:54 PM Tom_L: eyes were really tired
10:59 PM rue_shop3: https://paste.debian.net/1124283/
10:59 PM rue_shop3: that works
10:59 PM Tom_L: and what's it do?
10:59 PM rue_shop3: its a LUT based FSM without the feedback register
11:00 PM Tom_L: seems you're off and running now..
11:00 PM rue_shop3: or quickly stumbling
11:01 PM Tom_L: you can include more than one change in a case statement
11:01 PM Tom_L: if you ever need to
11:01 PM rue_shop3: yes, I wanted the format to be compact and clean
11:01 PM rue_shop3: that result is almost as far from it as you can get
11:02 PM Tom_L: 3'b001: begin Muxout = D[3:0]; an [3:0] = 4'b1000; end
11:02 PM Tom_L: i'm changing 2 registers in that one
11:02 PM rue_shop3: yea, I dont want the begin, end, and must of the bits in the middle
11:02 PM rue_shop3: I just want to specify the value
11:03 PM Tom_L: you may be able to do it without the begin.. end
11:03 PM Tom_L: i haven't tried it
11:03 PM rue_shop3: there is another way to do this but I dont know how to write it yet
11:04 PM rue_shop3: you have a whole bunch of values behind tristate buffers
11:04 PM rue_shop3: you only enable one of the buffers and it lets thru that value
11:06 PM Tom_L: ok, enough for one day
11:06 PM Tom_L: gnite
11:06 PM rue_shop3: haha, gnight
11:06 PM Tom_L: don't stay up all night...
11:07 PM Tom_L: you still gotta work :)
11:15 PM rue_shop3: er, right
11:15 PM rue_shop3: and supper
11:15 PM rue_shop3: arg
11:15 PM rue_shop3: I"m not sure how to phrase the feedback latch...
11:18 PM rue_shop3: if this works I'd love to see how it wires it
11:19 PM Tom_L: heh
11:19 PM rue_shop3: it... might have worked?
11:20 PM rue_shop3: I need to slow down my clock...
11:20 PM rue_shop3: compiling...
11:23 PM rue_shop3: haha yea
11:23 PM rue_shop3: workin
11:24 PM rue_shop3: yea, thats totally right
11:28 PM rue_shop3: I'll post image in a while here
11:41 PM rue_mohr: http://ruemohr.org/~ircjunk/tempimage/lutfsm.png
11:41 PM rue_mohr: if you squint
11:41 PM rue_mohr: you can see the datapath from FBO to the D flipflop, and back to FBI
11:41 PM rue_mohr: (feedback out, feedback in)