#garfield Logs
Jan 01 2020
#garfield Calendar
12:00 AM Tom_L: maybe they'll really go off then
12:06 AM rue_mohr: lights flickering, need to go shut down compressor
12:10 AM rue_mohr: happy new year!
12:11 AM rue_mohr: I got distracted
01:24 AM rue_mohr: happy new year!
01:39 AM rue_mohr: Tom_L, still there?
02:08 AM rue_mohr: happy new year!!!!
06:19 AM Tom_L: am now
04:53 PM rue_mohr: I wonder if I should try that internet card upgrade on the router
04:53 PM Tom_L: doesn't sound like a great idea
04:53 PM rue_mohr: I couldn't sleep last night, tonight and tommorowo are going to be a mess
04:54 PM Tom_L: smells like trouble
04:54 PM Tom_L: back to work tomorrow
04:54 PM rue_mohr: I got the drivers compiled in, and its been running the new kernel with them
04:54 PM Tom_L: spent the days off doing bookwork
04:55 PM rue_mohr: well that atleast get that out of the way
04:55 PM Tom_L: does the os see it?
04:55 PM rue_mohr: no, but they are still on the desk
04:55 PM Tom_L: got all my end of year done
04:55 PM rue_mohr: just in time
04:55 PM Tom_L: and updated the tax tables for next year
04:56 PM Tom_L: that was a bitch
04:56 PM rue_mohr: I made a bunch of progress across a bunch of things
04:56 PM Tom_L: due to changes in immigration laws etc
04:56 PM rue_mohr: but I spread out so much I'm not sure whats the master lead
04:56 PM Tom_L: and who gets a free ride this year
04:57 PM rue_mohr: I better have breakfast
04:57 PM rue_mohr: and move around for a while
04:57 PM Tom_L: mac n cheese with weiners
04:57 PM rue_mohr: do someting that doesn't involve a chair
04:57 PM Tom_L: with pigs in a blanket
04:57 PM rue_mohr: gee whiz, not for breakfast
04:58 PM Tom_L: scrambled egg with cut up hotdog with cheese melted over the top
04:59 PM rue_mohr: thats much much closer
05:00 PM Tom_L: z has been a bit more scarce lately
05:00 PM rue_mohr: my goals for this year are to upgrade the shop drillpress, finish the large cnc (hahaha "finish") and get the mecha rings assembled
05:00 PM rue_mohr: yea
05:01 PM rue_mohr: maybe we need to be more captivating
05:01 PM Tom_L: not me
05:01 PM rue_mohr: maybe he just needs a batter internet connection
05:01 PM Tom_L: i entertain myself
05:01 PM rue_mohr: :)
05:02 PM Tom_L: got my happy new year free drink at QT today
05:02 PM Tom_L: local gas/convenience store
05:03 PM Tom_L: i get free tanks of gas with their rewards card
05:03 PM Tom_L: takes a couple months but then YAY!
05:13 PM rue_mohr: :)
05:14 PM Tom_L: grocery store does it too but the points expire every month
05:14 PM Tom_L: these last a year
05:15 PM Tom_L: so now i just need a fpga card to show up on my door step
05:15 PM rue_mohr: have anything you want to complete by the end of 2020
05:17 PM rue_mohr: hey the spartin 6
05:17 PM rue_mohr: I read on one of the sheets that the min clk rating is 400Mhz
05:17 PM rue_mohr: and that they have a pll
05:17 PM rue_mohr: which we must not be turning on yet
05:19 PM Tom_L: min 400Mhz? these have a 50Mhz osc on them
05:19 PM rue_mohr: yea
05:19 PM rue_mohr: and a pll in them
05:19 PM Tom_L: my 68332 had a pll
05:20 PM Tom_L: you could burn em up if you wanted to
05:20 PM rue_mohr: the pll must be able to do 8x
05:20 PM Tom_L: once i figure out the subsystems, i'll ask the mesa guy if he uses any of them
05:21 PM Tom_L: he's a nice guy and has been doing it for many years
05:21 PM Tom_L: sent me a bunch of free boards
05:21 PM Tom_L: stuff he couldn't sell due to either being for test or had a broken header etc
05:22 PM Tom_L: and he uses spartan6 on them
05:24 PM rue_mohr: k
05:24 PM rue_mohr: your probably a few weeks out from getting your baord
05:28 PM Tom_L: i'm sure
05:29 PM Tom_L: that guy didn't seem to be in any rush
05:29 PM rue_mohr: you gonna start at the top of your demos and work your way thru?
05:29 PM Tom_L: i was gonna convert a couple to work on my current board but haven't yet
05:30 PM Tom_L: it's got ps2 & 7 seg so it should
05:30 PM Tom_L: unless it runs out of gates
05:30 PM rue_mohr: your kinda flip-clopping between verilog and vhdl eh?
05:30 PM rue_mohr: hah, I cant type anymore...
05:30 PM Tom_L: yeah i'd like to know both
05:30 PM Tom_L: seems most examples are verilog
05:31 PM Tom_L: and it's probably the easier of the 2 to pick up on
05:31 PM Tom_L: but knowing how to structure both to do the same thing is a goal
05:31 PM rue_mohr: I'm gonna stick with verilog for a while anyhow
05:31 PM Tom_L: that's fine
05:34 PM rue_mohr: I'm torn... tweaking this software I'm doing
05:37 PM Tom_L: may go relax. eyes can't focus after being at it for 2 days
05:37 PM rue_mohr: http://ruemohr.org/~ircjunk/tempimage/Untitled.png
05:37 PM rue_mohr: the dialog box
05:37 PM rue_mohr: I was playing with the prompt being black on a white background, but that doesn't really work out
05:38 PM rue_mohr: I'm pondering white on a white background...
05:38 PM rue_mohr: I dont think that'll play out either
05:38 PM Tom_L: white/grey
05:38 PM rue_mohr: grey might be some work..., but I can.
05:40 PM Tom_L: should show you my old dos program
05:40 PM rue_mohr: color?
05:40 PM Tom_L: yeah
05:44 PM Tom_L: http://tom-itx.no-ip.biz:81/~webpage/temp/main_menu.jpg
05:47 PM Tom_L: http://tom-itx.no-ip.biz:81/~webpage/temp/input.jpg
05:47 PM rue_mohr: nice, would it allow ya to use arrow keys or just the item number?
05:47 PM Tom_L: arrow
05:47 PM Tom_L: both
05:47 PM rue_mohr: my old ones are just the item number
05:47 PM rue_mohr: nice
05:47 PM Tom_L: figured you might recognize the 2nd one
05:47 PM rue_mohr: :)
05:47 PM rue_mohr: I dont even kow which state he's in now
05:48 PM Tom_L: i do most everything with that program
05:48 PM rue_mohr: still eh?
05:49 PM Tom_L: yes
05:49 PM rue_mohr: BGI?
05:49 PM Tom_L: was updating it for the tax today
05:49 PM Tom_L: bgi?
05:49 PM rue_mohr: borland grphic inteface
05:49 PM Tom_L: clipper
05:49 PM rue_mohr: huh
05:49 PM Tom_L: a compiled dbase language
05:49 PM rue_mohr: wonder if its bgi deep under there
05:49 PM Tom_L: c
05:50 PM Tom_L: you can hook into asm, pascal, c etc
05:50 PM Tom_L: it's more like pascal
05:50 PM rue_mohr: yea, the color theme is right in line with the bgi stuff
05:50 PM Tom_L: i made that up
05:51 PM rue_mohr: what level is th interface?
05:51 PM rue_mohr: like, boxes and textfields, or ?
05:51 PM Tom_L: yeah
05:51 PM rue_mohr: bgi lets you design like a gui
05:51 PM Tom_L: i can do just about anything i want with it
05:52 PM Tom_L: but it's dos so it's dos tech
05:52 PM rue_mohr: nice, I'm working up from scratch with linux ansi escape codes
05:52 PM Tom_L: fread fwrite etc
05:52 PM Tom_L: i did my printers with esc codes etc
05:52 PM rue_mohr: hmm
05:52 PM Tom_L: if you can't access a file with the database functions, just fopen it
05:53 PM rue_mohr: this thing I'm doing was BASIC back in 98
05:53 PM rue_mohr: I porte it to C and linux
05:53 PM Tom_L: i read/write text files, csv for import to other stuff etc
05:53 PM rue_mohr: and I'm trying to get rid of the old conio libraries
05:53 PM Tom_L: i used to remember how to make libs with it
05:53 PM Tom_L: i have one i use but forgot how to build them
05:54 PM Tom_L: basically make an .obj file and then combine them into a lib file
05:54 PM Tom_L: it was at the beginning of oops
05:54 PM Tom_L: some things are kindof oops ish
05:55 PM Tom_L: code blocks etc
05:55 PM Tom_L: i did a complete point of sale with it once
05:55 PM Tom_L: for my bud's hobby shop
05:56 PM Tom_L: imported inventory from his supplier's files so he didn't have to type in all his inventory
05:56 PM Tom_L: did barcode labels for him etc
05:58 PM Tom_L: i tried to convert this to windows once but didn't like what i was getting
05:58 PM Tom_L: dos is way faster for me
06:17 PM rue_mohr: its amazing how gui ads a huge heap of just gui handling code
06:17 PM rue_mohr: ok an item on my "every day " list is done, the "add water to fishtank" its full now
06:17 PM rue_mohr: yay
06:18 PM rue_mohr: gonna go pull out blackberries and beans..
06:19 PM polprog: cant sleep so im coming up with creative ideas to disrupt a cvbs signal
06:19 PM polprog: i could inject noise into several lines from x to y
06:20 PM polprog: i did generate composite video with an avr, so counting the lines with an stm should be fairly easy
06:20 PM polprog: happy new year btw
06:20 PM polprog: did you have any parties on the NYE?
06:37 PM Tom_itx is now known as Tom_L
07:47 PM rue_shop1: cvbs?
07:47 PM rue_shop1: gee I was partying every hour for about 4 hours there
07:47 PM rue_shop1: nobody else really joined in
07:47 PM rue_shop1: miss the old days
07:48 PM Tom_L: composite video
07:48 PM Tom_L: yeah it's not like it used to be
07:48 PM Tom_L: i think it would be cool to send txt to a vga with the fpga
07:49 PM Tom_L: or something
07:50 PM rue_mohr: your right
07:50 PM rue_mohr: we need ram access
07:50 PM rue_mohr: who wants to write the character generator rom?
07:50 PM Tom_L: that could be a first 'major' project
07:50 PM rue_mohr: I'd like to look into how to turn on the pll
07:51 PM rue_mohr: there is lots of stuff
07:51 PM rue_mohr: but I have to let where I'm at sink in
07:51 PM Tom_itx: https://www.xilinx.com/support/documentation/user_guides/ug382.pdf
07:54 PM Tom_itx: https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v3_1/clk_wiz_gsg521.pdf
07:55 PM Tom_itx: dunno if that's part of webpack or not
07:55 PM Tom_L: says it is
07:58 PM Tom_L: i don't see it
08:01 PM rue_mohr: I'd figure its done in the verilog
08:01 PM rue_mohr: but I can see if its not
08:01 PM rue_mohr: like an avr
08:04 PM Tom_L: ise 14.4 so we should have it unless it's an extra download
08:04 PM Tom_itx: https://www.xilinx.com/products/intellectual-property/clocking_wizard/clocking_wizard-software-requirements.html
08:05 PM rue_mohr: hehe 18G and it might not be included?
08:05 PM Tom_L: :)
08:07 PM Tom_L: says it's included
08:07 PM rue_mohr: https://www.xilinx.com/support/documentation/user_guides/ug382.pdf
08:07 PM rue_mohr: ?
08:09 PM rue_mohr: hmm I think this is a few steps over my head
08:15 PM Tom_itx: i think it's there
08:15 PM Tom_itx: i should open a fpga project instead of the cpld so it may show up
08:16 PM Tom_itx: yes
08:16 PM Tom_L: wanna find it?
08:16 PM rue_mohr: where...
08:16 PM rue_mohr: 1 min
08:17 PM Tom_L: haha
08:17 PM Tom_L: :)
08:17 PM rue_shop3: click where?
08:17 PM Tom_L: you find it :D
08:17 PM Tom_itx: open blinky project
08:18 PM rue_shop3: I have my pwm project up
08:18 PM Tom_itx: the 3 blocks beside the main program file in the list
08:18 PM Tom_itx: right click
08:18 PM Tom_itx: new source
08:18 PM Tom_itx: ip Core generator.....
08:18 PM Tom_itx: give it a name
08:19 PM Tom_itx: ready?
08:19 PM Tom_itx: click next
08:19 PM Tom_itx: in the list, open FPGA features and design
08:19 PM Tom_itx: clocking...
08:19 PM Tom_itx: clocking wizard
08:20 PM rue_shop3: wow its taking its time
08:20 PM rue_shop3: ok clocking wizard
08:20 PM rue_shop3: gee this is burried
08:20 PM Tom_itx: finally opens up a whole new screen full of crap to get you in trouble
08:21 PM rue_shop3: more waiting...
08:21 PM Tom_L: one of these days you'll make me find ALL the features it has
08:21 PM rue_shop3: AAAH I'm being attacked by a wizard!
08:22 PM Tom_L: carry on
08:23 PM rue_shop3: my input is 50Mhz....
08:24 PM rue_shop3: it looks like doubling it is easy...
08:24 PM rue_shop3: hmm I can have a bunch of them
08:25 PM rue_shop3: it doesn't mind 400Mhz
08:27 PM Tom_L: :)
08:27 PM Tom_L: it only shows the tools that are available for the chip associated with the project
08:28 PM rue_shop3: ok I clicked generate
08:28 PM rue_shop3: from what I can tell I need to modify my verilog src to pull from that internal clock instead of the clk input pin
08:28 PM Tom_L: should add another file to the project
08:28 PM rue_shop3: :/ yea, its working on it
08:28 PM rue_shop3: maybe I"ll let it do that and go make supper
08:28 PM Tom_L: k
08:29 PM Tom_L: more toys to play with
08:31 PM Tom_L: creates an .xco file
08:33 PM Tom_itx: https://www.youtube.com/watch?v=n-fERTjEQDs
08:34 PM Tom_itx: 'gadget factory' part 2-3 and likely other videos on it
08:34 PM Tom_itx: google it
08:43 PM Tom_L: yeah you will map your 'clk_xx' signal to the pin you assign to the output of the pll clock
08:51 PM rue_mohr: yea, watching a video
08:53 PM rue_mohr: drat the video I'm watching is vhdl
08:55 PM Tom_L: good fer ya
08:56 PM rue_mohr: I'm gonna need to knock myself out early, if I have any hope of waking up on time to get to work
08:57 PM rue_mohr: ok, the alarm speakers are working
08:57 PM Tom_L: yeah i'm goin pretty soon too but i won't sleep for a while no matter what
08:57 PM rue_mohr: yea, I thik I could easily be up till 3am
08:58 PM Tom_L: when they gonna look over your truck again?
09:08 PM rue_shop3: so NAPA cant get another set of gears
09:08 PM rue_shop3: I'm ordering another set from the other auto shop, and I'll see if they measure up then talk to them about the options forward
09:08 PM rue_shop3: cause they cant find a cover
09:09 PM rue_shop3: ERROR:HDLCompiler:532 - "/files/programming/fpga/xilinx/spartin6/stateMachine/blink.v" Line 53: Index <21> is out of range [19:0] for signal <clkdown>.
09:09 PM rue_shop3: v3_6/generate/run_legacy_tcl_flow.tcl" line 47)ERROR:sim - Unable to evaluate Tcl file:
09:09 PM rue_shop3: ERROR:sim - Failed executing Tcl generator.
09:09 PM rue_shop3: ERROR:sim - Failed to generate 'clockgen'. Failed executing Tcl generator.
09:09 PM Tom_L: you don't have a sim set up
09:09 PM rue_shop3: so, I guess no clocks for me
09:09 PM Tom_L: i'm not sure how to do that yet
09:10 PM Tom_L: requires some sim files etc i dunno about yet
09:10 PM Tom_L: i'd watch all 3 of those videos
09:10 PM Tom_L: will probably tell you how
09:11 PM rue_shop3: it didn't add a .v file to the project like it said it would
09:11 PM Tom_L: different file extension
09:11 PM Tom_L: i forget what it said
09:11 PM rue_shop3: er
09:11 PM Tom_L: and no it won't unless it passes
09:11 PM rue_shop3: ok wait, I
09:11 PM rue_shop3: had an old oops in my source
09:12 PM Tom_L: creates an .xco file
09:12 PM Tom_L: i think that's what it said
09:13 PM rue_shop3: it didnt
09:14 PM Tom_L: it will probably create it in that sub directory
09:14 PM rue_shop3: ./ipcore_dir/tmp/_cg/clockgen.xco
09:15 PM Tom_L: what's it look like?
09:16 PM rue_shop3: # BEGIN Project Options
09:16 PM rue_shop3: SET addpads = false
09:16 PM rue_shop3: SET asysymbol = true
09:16 PM rue_shop3: SET busformat = BusFormatAngleBracketNotRipped
09:16 PM rue_shop3: SET createndf = false
09:16 PM rue_shop3: SET designentry = Verilog
09:16 PM rue_shop3: SET device = xc6slx16
09:16 PM rue_shop3: SET devicefamily = spartan6
09:16 PM rue_shop3: ...
09:17 PM Tom_L: http://tom-itx.no-ip.biz:81/~webpage/xilinx/New_Board/EX9-VGA/ipcore_dir/CLK_DIV.xco
09:17 PM Tom_L: there's one for the vga project
09:18 PM Tom_L: from the same wizard
09:19 PM rue_shop3: I wonder if you even need the tcl stuff
09:19 PM Tom_L: what is it?
09:19 PM rue_shop3: its ui switches
09:19 PM rue_shop3: I think
09:20 PM rue_shop3: the tcl script is supposed to set stuff up
09:20 PM Tom_L: http://tom-itx.no-ip.biz:81/~webpage/xilinx/New_Board/EX9-VGA/ipcore_dir/CLK_DIV.v
09:20 PM rue_shop3: dunno what
09:21 PM rue_shop3: they are dividing the clock, not using the pll to multiply it
09:21 PM Tom_L: hmm
09:22 PM Tom_L: well we did find the tool to do it
09:22 PM rue_shop3: yup
09:22 PM Tom_L: just not sure which end to dig with yet
09:22 PM rue_shop3: if you did it, it might work
09:22 PM Tom_L: no bets on that
09:24 PM rue_shop1: i have an awefull headache
09:24 PM rue_shop1: think its cause I know i got work tommorow?
09:24 PM rue_shop1: I'm not being usefull right now anyhow
09:24 PM rue_shop1: going to work is just fine
09:25 PM Tom_L: https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v6_0/pg065-clk-wiz.pdf
09:26 PM Tom_L: Clocking Wizard helps create the clocking circuit for the required output clock frequency, phase, and duty cycle using a mixed-mode clock manager (MMCM)(E2/E3/E4) or phase-locked loop (PLL)(E2/E3/E4) primitive.
09:26 PM Tom_L: maybe you need to select a different clock source in the wizard
09:29 PM Tom_L: look around P21
09:30 PM Tom_L: no, those may just be errors
09:30 PM rue_mohr: it didn't give an input optiont ath i recall, so I presume the fpga has a clk input
09:31 PM Tom_L: the source may be internal for this, i'm not sure
09:40 PM Tom_L: http://tom-itx.no-ip.biz:81/~webpage/temp/xilinx/pg065-clk-wiz.pdf
09:40 PM Tom_L: i saved that last one there
09:40 PM Tom_L: newer version than ise but probably quite similar
09:41 PM Tom_L: vivado covers newer than spartan6 products
10:02 PM Tom_L: <pcw_home> I have only used the DPLL (which can do N/M frequency multiplication/division)
10:11 PM Tom_itx: https://www.xilinx.com/support/documentation/application_notes/xapp854.pdf
10:12 PM Tom_itx: https://www.xilinx.com/support/documentation/user_guides/ug382.pdf
10:13 PM Tom_itx: The Digital Frequency Synthesizer (DFS) provides a wide and flexible range of output frequencies based on the ratio of two user-defined integers, a multiplier (CLKFX_MULTIPLY) and a divisor (CLKFX_DIVIDE). The output frequency is derived from the input clock (CLKIN) by simultaneous frequency division and multiplication. The DFS feature can be used in conjunction with or separately from the DLL feature of the DCM. If the DLL is not used, then
10:13 PM Tom_itx: there is no phase relationship between CLKIN and the DFS outputs
10:13 PM Tom_itx: just one example
10:17 PM Tom_L: enough for one day.
10:17 PM Tom_L: gnite
10:22 PM rue_: odd
10:22 PM rue_: switch mentally imploded
10:28 PM Tom_L: dunno if you saw ^^ but pcw said he uses the dpll for freq div/mux
10:28 PM Tom_L: and he's never used that wizard