#garfield Logs

Dec 31 2019

12:36 AM rue_shop1: Tom_L,
12:41 AM rue_shop1: do you know if the oil goes thru the filter on the output of the pump?
12:41 AM rue_shop1: surely the oil isn't on the pump intake
04:10 AM rue_shop1: pcf8578
05:00 AM Tom_L: not sure
05:00 AM Tom_L: figure the summary page out and let me know :)
05:18 AM Tom_L: As this is a free software, that is how it works in this environment, as it is a part of terms and conditions that are set by marketing.
05:24 AM rue_shop1: I got pwm
05:24 AM rue_shop1: its glitch-inclusive
05:36 AM Tom_L: checking it with your new scope?
11:49 AM rue_bed: didn't do that one
11:49 AM rue_bed: oh I didn't show ya
11:49 AM rue_bed: give me time :)
11:49 AM rue_bed: ugh its 9:30am
12:12 PM Tom_L: no, it's afternoon now
04:03 PM Tom_itx is now known as Tom_L
09:37 PM rue_mohr: your a few hours out ruight?
09:38 PM Tom_L: huh?
09:39 PM Tom_L: it's 9:32
09:39 PM rue_mohr: I need to figure out how to shoout happy new year to
09:39 PM rue_mohr: 2 hours ahead
09:39 PM Tom_L: unless i find something to do soon i'm not gonna be up for it anyway
09:40 PM rue_mohr: oh well
09:40 PM rue_mohr: 3
09:40 PM rue_mohr: 2
09:40 PM rue_mohr: 1 ahppy new year!
09:41 PM rue_mohr: oops, well, hmm
09:43 PM rue_mohr: https://github.com/ZipCPU/cordic/blob/master/rtl/quarterwav.v
09:43 PM rue_mohr: data tables for fpga
09:44 PM rue_mohr: https://stackoverflow.com/questions/36366075/create-a-lookup-table-using-verilog-modelsim
09:44 PM rue_mohr: hmm
09:50 PM Tom_L: what you tryin to do with that?
10:03 PM rue_mohr: lookup table for a state machine
10:17 PM Tom_L: what's the difference in the different types of state machines?
10:17 PM Tom_L: are they similar to ladder logic?
10:18 PM Tom_L: i don't know much about ladder logic either
10:28 PM Tom_itx: https://verilogguide.readthedocs.io/en/latest/verilog/fsm.html
10:37 PM rue_mohr: so state machines can be used to detect and generate sequences
10:37 PM rue_mohr: they take a number of events into them, and emit events
10:38 PM Tom_L: what's a practical use for one?
10:39 PM rue_mohr: turning changes in encoder bits into forward/reverse pulses
10:40 PM rue_mohr: any program with a user interface
10:40 PM rue_mohr: (its a bit abstract on that
10:40 PM rue_mohr: the huge mess of if-else isn't practical for big stuff
10:41 PM Tom_L: ok lemme give you a for instance...
10:41 PM Tom_L: http://linuxcnc.org/docs/2.8/html/man/man9/lut5.9.html
10:42 PM Tom_L: ?
10:42 PM rue_mohr: I used a state machine for a guy to help work out the crank angle on this V10
10:42 PM Tom_L: i'm using one of those on the mill iirc
10:42 PM Tom_L: is that considered a state machine?
10:42 PM rue_mohr: I wonder where the 6th input went.....
10:43 PM rue_mohr: a lut isn't a state machine
10:43 PM Tom_L: but you were working on a lookup table...
10:43 PM Tom_L: what's the difference?
10:43 PM rue_mohr: a state machine can be used to turn forward/backswards step events into stepper coil sequences
10:44 PM rue_mohr: a state machine can be made from a lookup table with a feedback register
10:46 PM Tom_L: seems perfect for a fpga but i still don't get it
10:46 PM rue_mohr: its what I want ed to do with the pld that I couldn't do
10:46 PM rue_mohr: so I went to fpga cause thats the only point they will let you in at
10:47 PM Tom_L: you should have enough gates now
10:47 PM rue_mohr: 18V22 programming isn't opensource toolchain
10:47 PM rue_mohr: yea
10:47 PM rue_mohr: I'm not sure how to set up a big arbitrary memory array
10:48 PM Tom_L: what is 18v22?
10:48 PM Tom_L: i found one the other day... if i can find it
10:48 PM rue_mohr: pld
10:48 PM Tom_L: in the mesa code
10:48 PM rue_mohr: its a rom bank with a feedback register
10:48 PM Tom_L: oh
10:48 PM Tom_L: i posted the examples outside the rar file
10:48 PM rue_mohr: can be used as discrete logic of a state machine
10:49 PM Tom_L: http://tom-itx.no-ip.biz:81/~webpage/xilinx/New_Board/
10:50 PM Tom_L: mmm i thought there was one as a ram controller but i guess not
10:57 PM rue_mohr: well,
10:57 PM rue_mohr: that spartin 6 board has a ram controller
10:57 PM Tom_L: i found one with a large table but dunno what it does
10:57 PM rue_mohr: I dont know how to interface with the ram
10:57 PM rue_mohr: lets see the alrge table
10:59 PM Tom_L: http://tom-itx.no-ip.biz:81/~webpage/rue/Xilinx/resrom.vhd
10:59 PM Tom_L: i dunno what it's for
11:00 PM Tom_L: there's another one there too
11:00 PM Tom_L: 512 len
11:02 PM rue_mohr: ah there we go
11:03 PM Tom_L: give you a clue?
11:03 PM Tom_L: that's vhdl though
11:03 PM rue_mohr: oh drat its vhdl
11:03 PM rue_mohr: looking for verilog
11:03 PM Tom_L: easy to convert
11:04 PM rue_mohr: not for me
11:06 PM Tom_itx: https://www.chipverify.com/verilog/verilog-arrays-memories
11:07 PM rue_mohr: thats not preloaded with values tho
11:08 PM Tom_itx: https://www.xilinx.com/support/documentation/user_guides/ug388.pdf
11:08 PM Tom_L: i don't care for their docs much
11:08 PM Tom_L: happy new year again!
11:08 PM rue_mohr: :)
11:11 PM Tom_itx: https://hackaday.com/2013/10/11/sdram-controller-for-low-end-fpgas/
11:11 PM rue_mohr: it has one on board
11:12 PM Tom_L: controller?
11:12 PM Tom_L: or ram
11:12 PM rue_mohr: the spartin 6 has a hardare ram controller
11:12 PM rue_mohr: thats one of its features
11:13 PM rue_mohr: thats why there is a ram chip on the baord
11:13 PM Tom_L: yeah i don't know how to access the built in features yet
11:13 PM rue_mohr: dunno either
11:13 PM rue_mohr: we should be googling that
11:13 PM Tom_L: 20 yrs ago we were worried about Y2K
11:14 PM rue_mohr: damn, it was that long ago
11:14 PM Tom_L: well it _is_ almost 2020
11:14 PM rue_mohr: wow, I still have the "there was no boom" youtube clip up
11:15 PM rue_mohr: somewhere its only been 2020 for 8 minutes
11:15 PM Tom_L: NY
11:15 PM Tom_itx: https://www.xilinx.com/support/documentation/user_guides/ug380.pdf
11:18 PM Tom_itx: https://numato.com/blog/spartan6-and-ddr-sdram-memory-your-first-ddr-interfacing-project/
11:18 PM Tom_L: different board but might have a clue
11:18 PM rue_mohr: first link is a dud
11:18 PM rue_mohr: its how to actually transfer config to it
11:20 PM Tom_L: memory interface wizzard
11:21 PM rue_mohr: maybe there was an example int eh qmtech stuff
11:30 PM Tom_itx: https://www.isy.liu.se/edu/kurs/TSEA83/kursmaterial/vhdl/spartan6_hdl.pdf
11:30 PM Tom_itx: maybe another dud i dunno
11:30 PM Tom_itx: scroll down to ram in the side pannel
11:32 PM rue_mohr: I'm sure it needs to be part of the source in the verilog?
11:32 PM Tom_itx: dunno yet
11:32 PM Tom_itx: https://danstrother.com/2010/09/11/inferring-rams-in-fpgas/
11:37 PM Tom_itx: https://www.xilinx.com/support/documentation/user_guides/ug383.pdf
11:37 PM Tom_L: spartan6 block ram resources
11:39 PM * Tom_L thinks rue_mohr jumped into the deep end of the pool
11:41 PM rue_mohr: got the directory all set up for pictures for the new year
11:42 PM Tom_L: that last one might be useful later on when i realize how to use them
11:43 PM rue_mohr: hmm
11:43 PM rue_mohr: I wonder if the loader can init memory from the flash
11:43 PM rue_mohr: I dont know if the flash chip has spare room
11:43 PM Tom_L: probably
11:43 PM Tom_L: how big is it?
11:44 PM Tom_L: the bit files are ~3-400k
11:45 PM rue_mohr: oh its mega
11:45 PM rue_mohr: megs
11:45 PM Tom_L: you can typically load at least 2 configs in it
11:45 PM rue_mohr: its like 512M
11:45 PM Tom_L: mesa uses a fallback config if the user config fails
11:45 PM Tom_L: the docs tell how to set that up
11:46 PM Tom_L: i'm a long ways from that though
11:56 PM rue_mohr: hmm
11:59 PM rue_mohr: odd the fireworks at 10:00 instead of midnight