#garfield Logs
Dec 01 2019
#garfield Calendar
12:34 AM rue_mohr: 2 correctsions and its working fine at 5khz
12:39 AM rue_mohr: I can push it later
02:16 AM rue_shop2: zh https://www.youtube.com/watch?v=zNGuuSKE1pY
02:22 AM rue_shop2: https://www.youtube.com/watch?v=qtZv96ciFIU
02:22 AM rue_shop2: hmmm
02:54 PM Tom_L: rue_mohr, what's a project you have in mind for the fpga?
02:55 PM Tom_L: we should 'study' together
02:55 PM Tom_L: if you had a debian 8 box it might work on that
02:55 PM Tom_L: <-- untested
02:59 PM Tom_L: i still need to figure out which file is the one to download... it isn't .bit
02:59 PM Tom_L: it said it compiled but no .bit file in the directory... there are other useable formats
03:17 PM Tom_L: JED or ISC for CPLD
03:44 PM Tom_L: .UCF is the pin map file
04:01 PM Tom_L: yay! successfully programmed a different file to it
04:03 PM Tom_L: bringing these project files up to date
04:18 PM rue_shop1: :) I need a working install
04:18 PM rue_shop1: hmm, state machine, let me thing
04:18 PM Tom_L: i got their demo files working
04:18 PM Tom_L: whole project built new
04:19 PM rue_shop1: pin file?
04:19 PM Tom_L: ^^
04:19 PM Tom_L: it's a JED file
04:19 PM Tom_L: for cpld
04:19 PM rue_shop1: interseting
04:19 PM rue_shop1: oooh
04:19 PM Tom_L: and probably ISC for cpld
04:19 PM rue_shop1: yea, I'm thiniking fpga
04:19 PM rue_shop1: k
04:19 PM Tom_L: err vise versa
04:19 PM rue_shop1: let me think something up
04:19 PM Tom_L: both those are cpld
04:19 PM rue_shop1: hows the flooring going?
04:20 PM Tom_L: depending on the standard used
04:20 PM Tom_L: next friday they come
04:20 PM Tom_L: so everything is a mess until then
04:20 PM Tom_L: i left my desk for wed or thur to take down
04:21 PM Tom_L: the log may still run but i'll probably be gone
04:21 PM Tom_L: i have riot mapped to here on my phone
04:21 PM Tom_L: that's the Tom_L[m]
04:21 PM Tom_L: well it shows up anywhere
04:24 PM Tom_L: ok that top.v test file works
04:24 PM Tom_L: but it's got a couple unexpected things
04:25 PM Tom_L: 2 leds are blinking i didn't expect
04:25 PM Tom_L: may be a mapping thing
04:27 PM Tom_L: downloader -> Impact project file: .IPF
04:27 PM Tom_L: extension
04:28 PM Tom_L: i don't really know what language my test is
04:28 PM Tom_L: their verilog test file looks different
05:47 PM Tom_L: their test is VHDL i figured that much out
05:48 PM Tom_L: verilog and VHDL are very similar
05:49 PM Tom_L: let's pick one and go with it...
05:50 PM Tom_L: i'll try to convert the files to the choice
05:51 PM Tom_itx: for example, this is VHDL:
05:51 PM Tom_itx: library ieee;
05:51 PM Tom_itx: use ieee.std_logic_1164.all;
05:51 PM Tom_itx:
05:51 PM Tom_itx: entity example_and is
05:51 PM Tom_itx: port (
05:51 PM Tom_itx: input_1 : in std_logic;
05:51 PM Tom_itx: input_2 : in std_logic;
05:51 PM Tom_itx: and_result : out std_logic
05:51 PM Tom_itx: );
05:52 PM Tom_itx: end example_and;
05:52 PM Tom_itx:
05:52 PM Tom_itx: architecture rtl of example_and is
05:52 PM Tom_itx: signal and_gate : std_logic;
05:52 PM Tom_itx: begin
05:52 PM Tom_itx: and_gate <= input_1 and input_2;
05:52 PM Tom_itx: and_result <= and_gate;
05:52 PM Tom_itx: end rtl;
05:52 PM Tom_itx: this is verilog:
05:52 PM Tom_itx: module example_and_gate
05:52 PM Tom_itx: (
05:52 PM Tom_itx: input_1,
05:52 PM Tom_itx: input_2,
05:52 PM Tom_itx: and_result);
05:52 PM Tom_itx:
05:52 PM Tom_itx: input input_1;
05:52 PM Tom_itx: input input_2;
05:52 PM Tom_itx: output and_result;
05:52 PM Tom_itx:
05:52 PM Tom_itx: wire and_temp;
05:52 PM Tom_itx:
05:52 PM Tom_itx: assign and_temp = input_1 & input_2;
05:52 PM Tom_itx:
05:52 PM Tom_itx: assign and_result = and_temp;
05:52 PM Tom_itx:
05:52 PM Tom_itx: endmodule // example_and_gate
05:53 PM Tom_L: .
05:53 PM Tom_L: i don't know which is better
06:14 PM Tom_L: the .v files must be HDL
06:14 PM Tom_L: afik
06:16 PM Tom_L: trying to add an led and keep getting errors :(
06:56 PM RonoldoMoon: rue_bed2: Hay!
06:58 PM Tom_L: moon
06:58 PM Tom_L: you know vhdl?
06:58 PM RonoldoMoon: me
06:58 PM Tom_L: or verilog
06:59 PM RonoldoMoon: no :(
06:59 PM rue_shop1: hey
06:59 PM RonoldoMoon: hey
06:59 PM Tom_L: rue_mohr!
06:59 PM rue_shop1: just made the block for trying to extrude silicone tubing
06:59 PM RonoldoMoon: ! :D
06:59 PM Tom_L: i'm stuck on a line and need some help!
07:00 PM RonoldoMoon: I need some help too rue_shop1 :P
07:01 PM Tom_L: take a number!
07:01 PM RonoldoMoon: #2 :)
07:02 PM Tom_L: http://tom-itx.no-ip.biz:81/~webpage/temp/xilinx/top.v
07:03 PM Tom_itx: ERROR:HDLCompilers:26 - "../top.v" line 34 unexpected token: 'led1'
07:03 PM Tom_L: can't figure that one out
07:04 PM Tom_L: it's declared
07:04 PM Tom_L: and in the module parameters
07:04 PM Tom_L: simple silly thing
07:06 PM rue_shop1: begin
07:06 PM rue_shop1: if (bn) begin
07:06 PM rue_shop1: ... end
07:06 PM Tom_L: but it didn't need it when just the D = 0; line was there
07:07 PM rue_shop1: but you added the if?
07:07 PM Tom_L: no
07:07 PM rue_shop1: huh
07:07 PM Tom_L: all i added was led /= bn;
07:07 PM rue_shop1: ok swap the two lines
07:07 PM Tom_L: d?
07:07 PM rue_shop1: the D=0 and the led1 lines
07:08 PM rue_shop1: if you require a begin, it will error out on D
07:08 PM Tom_L: same error
07:08 PM Tom_L: unexpected token
07:08 PM rue_shop1: says unexteded D or unextedted led1
07:08 PM Tom_L: led
07:08 PM Tom_L: 1
07:08 PM rue_shop1: I think its expecting the word begin
07:09 PM Tom_L: nope
07:09 PM Tom_L: added it inside the other begin and same error
07:10 PM Tom_L: it's mapped in the pin file too
07:11 PM rue_shop1: so right now you have if (bn) begin D = 0; led1 /=bn; end
07:11 PM Tom_L: yes
07:11 PM rue_shop1: and they dont need to have registers?
07:11 PM Tom_L: i tried that too
07:12 PM Tom_L: had output led1;
07:12 PM Tom_L: reg led1'
07:12 PM Tom_L: ;
07:12 PM rue_shop1: hmm I need to see more examples
07:12 PM Tom_itx: now let me show you how verilog does it
07:12 PM rue_shop1: I need to spurt some silicone into this water while its still warm
07:13 PM Tom_itx: entity Xc95Test is
07:13 PM Tom_itx: Port ( mclk : in std_logic;
07:13 PM Tom_itx: bn : in std_logic;
07:13 PM Tom_itx: ld : out std_logic;
07:13 PM Tom_itx: ldg : out std_logic;
07:13 PM Tom_itx: btn : in std_logic_vector(3 downto 0);
07:13 PM Tom_itx: swt : in std_logic_vector(7 downto 0);
07:13 PM Tom_itx: led : out std_logic_vector(7 downto 0);
07:13 PM Tom_itx: an : out std_logic_vector(3 downto 0);
07:13 PM Tom_itx: ssg : out std_logic_vector(6 downto 0)
07:13 PM Tom_itx: );
07:13 PM Tom_itx: end Xc95Test;
07:13 PM Tom_L: wait...
07:14 PM Tom_itx: begin
07:14 PM Tom_itx: ldg <= '1';
07:14 PM Tom_itx: ld <= not bn;
07:14 PM Tom_itx: led(7 downto 0) <= swt(7 downto 0);
07:14 PM Tom_itx: .....
07:14 PM Tom_itx: end
07:14 PM Tom_itx: it's "ld" in that file
07:15 PM Tom_itx: err that's VHDL
07:20 PM Tom_L: http://tom-itx.no-ip.biz:81/~webpage/temp/xilinx/Xc95Test.vhd
07:20 PM Tom_L: there's another test file (unrelated)
07:21 PM Tom_L: http://tom-itx.no-ip.biz:81/~webpage/temp/xilinx/BtnDemo.vhd
07:21 PM Tom_L: an even simpler one with just the button and led
07:21 PM rue_shop1: damnit 110% fail
07:21 PM rue_shop1: freaking mess
07:21 PM rue_shop1: arg
07:22 PM Tom_L: what are you fixing?
07:22 PM rue_shop1: trying to extrude silicone tube
07:22 PM Tom_L: oh
07:22 PM rue_shop1: cause I cant get sth damn stuff in the size I need
07:22 PM rue_shop1: arg, bleeding too
07:23 PM Tom_L: plug that with silicone
07:23 PM rue_shop1: biab have to clean up
07:24 PM Tom_L: i think i like the format of VHDL over verilog
07:29 PM rue_mohr: arg
07:29 PM rue_mohr: ok, so wait
07:29 PM rue_mohr: what is the .v file, vhdl or verilog?
07:29 PM Tom_L: i'm not entirely sure HDL i think
07:29 PM rue_mohr: and vhd is?
07:30 PM rue_mohr: vhdl...
07:30 PM Tom_L: vhdl
07:30 PM rue_mohr: ok
07:30 PM Tom_L: verilog looks alot like it
07:30 PM rue_mohr: so, were gonna use which?
07:30 PM Tom_L: i don't care
07:30 PM Tom_L: i just had these
07:30 PM rue_mohr: eek, I need to start with 1 road
07:30 PM Tom_L: yeah that's why i asked earlier
07:30 PM Tom_L: i don't care which one i use
07:30 PM Tom_L: vhdl looks simpler to follow
07:31 PM rue_mohr: zhanx, get the links?
07:31 PM zhanx: got them
07:31 PM rue_mohr: thoughts?
07:31 PM zhanx: watching now
07:32 PM rue_mohr: trying to extude silicone was a disaster, the stuff is too thick, more was getting past eh piston than going to into the mold
07:33 PM rue_mohr: and more was going at the mold than comming out of it
07:33 PM rue_mohr: and the hole in the middle just *didn't*
07:34 PM rue_mohr: Tom_L, I have xilinx on my sitdown list
07:34 PM Tom_L: yeah
07:34 PM rue_mohr: go thru the help and tutorials
07:34 PM Tom_L: i found the libs that go with it
07:34 PM rue_mohr: maybe *just* the input and output
07:34 PM rue_mohr: I didn't find them in debian for 10
07:35 PM Tom_itx: library IEEE;
07:35 PM Tom_itx: use IEEE.std_logic_1164.all;
07:35 PM Tom_itx: use IEEE.std_logic_textio.all;
07:35 PM Tom_itx: use IEEE.std_logic_arith.all;
07:35 PM Tom_itx: use IEEE.numeric_bit.all;
07:35 PM Tom_itx: use IEEE.numeric_std.all;
07:35 PM Tom_itx: use IEEE.std_logic_signed.all;
07:35 PM Tom_itx: use IEEE.std_logic_unsigned.all;
07:35 PM Tom_itx: use IEEE.math_real.all;
07:35 PM Tom_itx: use IEEE.math_complex.all;
07:35 PM Tom_itx: library STD;
07:35 PM Tom_itx: use STD.textio;
07:35 PM Tom_L: use those in the declaration at the top for VHDL
07:35 PM rue_mohr: what? no, missing things like libxp6.so
07:35 PM Tom_L: i know, you won't find them
07:36 PM Tom_L: unless you go to unstable and get them
07:36 PM Tom_L: maybe
07:36 PM rue_mohr: yea, there are a few directions I might be able to go
07:36 PM Tom_L: i found one for something else there
07:36 PM rue_mohr: I never woke up today
07:36 PM rue_mohr: the whole day my eyes been snapping shut
07:36 PM Tom_L: i went down this path instead of 'fix xilinx on linux' path
07:37 PM Tom_L: unstable might have the libs
07:37 PM rue_mohr: I'm going to take a look at what their using for the tang nano too
07:37 PM rue_mohr: AND my new video card arrived
07:37 PM Tom_L: link to tang?
07:37 PM rue_mohr: like *the next day*
07:37 PM Tom_L: code base
07:38 PM rue_mohr: https://www.aliexpress.com/item/4000329870934.html
07:40 PM Tom_itx: they use the .v files
07:40 PM Tom_itx: which is HDL
07:40 PM Tom_itx: https://github.com/sipeed/Tang-Nano-examples/blob/master/example_lcd/lcd_pjt/src/VGAMod.v
07:40 PM rue_mohr: vhdl = vdl?
07:40 PM Tom_itx: vhdl = .vhd
07:40 PM Tom_itx: hdl = .v i think
07:41 PM Tom_itx: dunno what verilog is
07:41 PM rue_mohr: heheh
07:41 PM rue_mohr: ok
07:41 PM rue_mohr: I needed to do two things
07:41 PM Tom_itx: i did figure out the file extensions of some of the xilinx files we need in the project
07:41 PM rue_mohr: the silicone thing and something else
07:41 PM zhanx: rue_mohr, I like it
07:41 PM Tom_itx: that led thing just doesn't make sense though
07:42 PM rue_mohr: zhanx, less the freaking extruder heaters he used, looks quite doable eh?
07:42 PM zhanx: yep
07:42 PM rue_mohr: Tom_itx, the xilinx board is on its way
07:42 PM Tom_itx: good
07:42 PM rue_mohr: prolly see it in another 2 weeks
07:42 PM Tom_itx: z, what diameter is that screw you made?
07:43 PM Tom_itx: rue_mohr, it'll be fun
07:43 PM Tom_itx: i need a chip socket and i can't find any of mine
07:43 PM Tom_itx: so i can make a plug for this board instead of dangling wires
07:44 PM rue_mohr: I seem to be spendy latley, should I burn another $12 on a tang?
07:44 PM Tom_itx: 24
07:44 PM zhanx: Tom_itx, 40mm
07:44 PM Tom_itx: send me one :D
07:44 PM Tom_itx: rue_mohr, i'd wait and see if you like the first one
07:44 PM rue_mohr: <z changed address> <should have address for tom>
07:45 PM rue_mohr: you know china, buy now, play later
07:45 PM Tom_itx: naw, i like what i have cause it's ready to go
07:45 PM Tom_itx: if i got another one i'd get the one with all the leds and buttons again
07:45 PM Tom_itx: with the spartain6 chip
07:46 PM Tom_itx: not much time to fiddle anymore
07:46 PM Tom_itx: but i can sit here and code til i fall asleep
07:48 PM Tom_itx: https://github.com/sipeed/Tang-Nano-examples
07:48 PM Tom_itx: rue_mohr, you should bookmark that
07:53 PM rue_shop1: I need to follow the tutorial on how to *everything* with it, pending
07:53 PM Tom_itx: yeah, i'm just gathering information
07:54 PM Tom_itx: i did get past the led but dunno if it works yet
08:04 PM rue_mohr: what ws the answer?
08:04 PM rue_mohr: ok I got 4 hours left to live
08:05 PM Tom_L: i didn't say it was working yet
08:06 PM Tom_itx: begin
08:06 PM Tom_itx: D = D + 1;
08:06 PM Tom_itx: if (bn) // Use as a counter reset
08:06 PM Tom_itx: D = 0; // Maybe should check a bit more often.
08:06 PM Tom_itx: led1 = 1;
08:06 PM Tom_itx: end
08:06 PM Tom_itx: but i can't compare it to the button
08:16 PM rue_mohr: kitty litter changed, supper started
08:17 PM rue_shop1: I have first pass on a new kernel for the new video card
08:17 PM rue_shop1: fixing network tester for work
08:22 PM Tom_L: do you optimize your kernels?
08:28 PM rue_mohr: kinda, I dont put in every peice of hardware I'll never have
08:29 PM rue_mohr: for the new video card, its easiest to jump to a new kernel version, helps with modules
08:31 PM Tom_L: the .v is older verilog files i think
08:33 PM Tom_L: this simple logic is pissin me off
08:33 PM rue_mohr: hmm
08:33 PM rue_mohr: clean slate?
08:41 PM Tom_L: it still doesn't like the comparison
08:50 PM Tom_L: ok maybe this time...
08:55 PM Tom_L: compiled and downloaded but didn't work
09:17 PM rue_shop1: 2 hours left
09:18 PM Tom_L: updating the rest of the demos
09:18 PM Tom_L: still didn't get the led to work right
09:38 PM rue_mohr: mmm supper
09:40 PM Tom_L: vhd file comments are '--'
09:40 PM rue_mohr: ok!
09:41 PM Tom_L: v file comments are //
09:42 PM Tom_L: i'm working on getting the a vhd file to do the same demo as the other one
10:25 PM Tom_L: ok pick it up again tomorrow...