#avr Logs

Sep 22 2022

09:41 AM twnqx: hm. unused logic inputs of 74LS... i read they should always have a pull-up if you want a logic 1, but logic 0 can be directly to ground?
09:53 AM qu1j0t3: i think so?
09:53 AM twnqx: 1-2mA for logic 1
09:53 AM qu1j0t3: ugh yeah i forgot how hungry they are
09:54 AM twnqx: this schematic is getting out of control :S and it only is a minimal piece of it all
09:55 AM twnqx: and only using less normal families like ACT, ALS, AS
09:57 AM twnqx: i wonder how to to breadboard it for tests.. 17 ICs (or similar, like oscillators) currently
09:57 AM qu1j0t3: oof.
09:58 AM qu1j0t3: my current proj had ~ 11 ics on a breadboard and in some ways it performed better than the pcb ;-)
09:58 AM qu1j0t3: that's my luck for ya
09:58 AM twnqx: does it feature frequencies up to 36mhz ny design? :D
09:58 AM twnqx: ny*
09:59 AM twnqx: guess i need to redo the pull-up resistors to adjust for currents
09:59 AM qu1j0t3: twnqx: No! it's a slow circuit
10:00 AM qu1j0t3: twnqx: yeah
10:00 AM twnqx: by my standard this is slow, too, but i guess it's pretty fast for the era
10:00 AM twnqx: though the 74ACT175 could handle 110MHz
10:00 AM qu1j0t3: twnqx: do you use resistor networks?
10:00 AM twnqx: only on a dip switch
10:00 AM qu1j0t3: might save space on pcb
10:00 AM twnqx: basically i place an individual pull-up resistor next to each bypass capacitor
10:01 AM twnqx: https://i.imgur.com/FMnH6sX.png this an older version of where i am at
10:02 AM twnqx: 4 layer PCB of course
10:02 AM qu1j0t3: pretty!
10:03 AM twnqx: the thing i am scared of
10:03 AM twnqx: is that that is probybly 10% of the end result
10:03 AM twnqx: if even that much
10:04 AM qu1j0t3: i'm 100% tht too; 2 layer. some chips optional (level shifters) https://pbs.twimg.com/media/Fbac2c7XkAYTigs?format=jpg&name=4096x4096
10:04 AM twnqx: :)
10:04 AM qu1j0t3: it was definitely not easy to do this on 2 layers, but there are only a couple of vias
10:04 AM qu1j0t3: handful*
10:05 AM twnqx: i think more than half of my current vias are for the GND cutout in the 5V layer along where i need to route clock signal on the top side, too :P
10:05 AM qu1j0t3: yeah doing ground fills meant a LOT of headaches
10:06 AM twnqx: i am also disappointed that most likely µATX size won't suffice
10:06 AM twnqx: full size ATX or even larger will be needed... not fun, pricewise
10:07 AM * qu1j0t3 nods
10:07 AM qu1j0t3: this was JLCPCB, about $1/board
10:07 AM twnqx: for how many?
10:08 AM qu1j0t3: 5
10:08 AM twnqx: nice
10:08 AM qu1j0t3: lucky i didn't get more, there were several bad bugs fixed with bodges
10:09 AM twnqx: that's why i want to breadboard this first - not even soldered
10:10 AM qu1j0t3: yes
10:10 AM qu1j0t3: i breadboarded this to death
10:11 AM qu1j0t3: and i checked kicad to death
10:11 AM qu1j0t3: but they still creep in
10:11 AM qu1j0t3: the errors were in kicad, not the breadboard
10:11 AM twnqx: uhhh
10:11 AM qu1j0t3: but there is a weird signal distortion on SOME Of the pcbs that i haven't tracked down yet
10:11 AM exp: why did you choose 2 layer?
10:12 AM qu1j0t3: because i'm a lunatic
10:12 AM exp: and personally i don't bother with breadboards anymore, almost everything i do is smt so i just buy the little adaptor boards and string those together on verboard
10:12 AM exp: right but 4 layer isn't much more expensive lol
10:12 AM twnqx: it... is
10:12 AM twnqx: when you start to hit 12x13 inch...
10:12 AM qu1j0t3: well, using tht is also a ... idiosyncratic choice now
10:12 AM qu1j0t3: but, that's my prototyping stockpile so
10:13 AM exp: twnqx: how much more? i am surprised if it's much at all
10:14 AM twnqx: with pcbway, 176$ for 5 vs. 243$
10:15 AM twnqx: (with leaded HASL, not even going after ENIG yet :P)
10:16 AM twnqx: ENIG is 190 vs 280
10:21 AM exp: i wonder why ENIG adds that much extra, i don't think the inner layers are plated before pressing are they?
10:21 AM exp: i guess i don't know, but i don't think so!
10:21 AM twnqx: no
10:22 AM twnqx: not on any PCB i had to drill up so far :P
10:22 AM exp: anyway that's a fairly significant difference i suppose
10:22 AM twnqx: you are actually right, never thought about that
10:23 AM exp: i typically target 4 layer to start with anyway, i typically order smaller PCBs in larger quantity and boy it solves a lot of problems having a ground plane or two
10:23 AM twnqx: yeah
10:24 AM twnqx: i hope i won't have to use 6 layers for this when it comes to the busses :P
10:27 AM twnqx: i once ordered PCBs in ENIG without solder resist on the bottom side so it could be used for better heat transfer
10:27 AM twnqx: the manufacturer was not amused...
10:28 AM twnqx: "hey, you forgot to send us the soldermask" "no..."
10:33 AM exp: lol
10:33 AM exp: did they re-quote you after that?
10:33 AM twnqx: no
10:36 AM twnqx: oh right, there was still 1 feature missign in the clock generation *sigh*
11:03 AM twnqx: i wonder if i can replace the nand with a nor, hmmm