#avr Logs

Sep 11 2020

12:07 AM TechChristoph: mornin all
05:14 AM polprog: [00:11] cehteh: well the time he spends on programming that shit would buy him 10000 ic's
05:15 AM polprog: this
05:15 AM polprog: its probably cheaper to slap some glue logic than to try and figure out how to do that in assembly
05:15 AM polprog: not to mention the programming cost (yeah you could order preprogrammed but its still hilarious)
06:17 AM cehteh: since atomic clock is involved i guess its not a mass product
06:18 AM vmt: yeah... i'd imagine sourcing atomic clocks en masse would probe to be problematic:D
06:18 AM vmt: prove even
06:18 AM Thrashbarg: bah just ask CuriousMarc :P
06:19 AM cehteh: still its easy to ise an AVR for that, but no need to use asm
07:47 AM polprog: just get a GPS module, Uncle Sam put atomic clocks in space for *free*
07:49 AM Thrashbarg: back in the day you could run a clock off broadcast PAL television because the colour carrier, sync, etc, were all pretty accurate. I *think* they were atomic clock accurate but I'm not certain
07:50 AM polprog: wow, i didnt know that
08:00 AM cehteh: well atomic clocks are now not totally unobtanium, when you really need one you can buy these for a couple hundreds to thousands bucks
08:01 AM cehteh: for lab equipment and such
08:03 AM vmt: so it would appear syncing your devices on gps time would render them pretty easily b0rk3dable
08:04 AM twnqx: not if you tell you ntpd to not accept large jumps
08:04 AM cehteh: lol
08:04 AM cehteh: soemtimes in physics experiments you need long time stable clocks with very godo accuracy
08:05 AM twnqx: but yeah, given code to generate data to transmit for faking GPS exists as open source, bad idea
08:05 AM cehteh: no jump no if's ...
08:10 AM vmt: no stores no writes
08:11 AM vmt: err reads even
08:11 AM twnqx: i actually wonder if he really wanted a 0.5Hz signal
08:13 AM cehteh: possibly some defined pulse
08:13 AM twnqx: if he implements what he said, he'll get a precise 50:50 square signal with 0.5hz
08:13 AM cehteh: anyway i bet you can find a prescaler/TOP thingy to run a timer at the right divisor
08:14 AM vmt: i don't think he cared that much about the hold time
08:14 AM vmt: at least from what i understood
08:14 AM cehteh: yes usually only one edge is interesting
08:14 AM twnqx: one, and only one, ever?
08:14 AM twnqx: not synchronized to anything`?
08:15 AM twnqx: nah, it makes no sense like that
08:15 AM vmt: that's how i understood it
08:15 AM vmt: he wanted to sync one edge exactly a second apart, though i am known to be confused often times so...
08:15 AM twnqx: oh well, he didn't describe enough
08:15 AM twnqx: or he missed tons of poitns
08:15 AM vmt: one, well the "other" edge
08:16 AM twnqx: anyway, his solution is probably among the worst
08:17 AM twnqx: i think an avr is among the last things i'd use for that
08:17 AM cehteh: also windering if there are very small and cheap FPGA's to implement such custom logic
08:17 AM twnqx: yes
08:17 AM cehteh: i may need something like that in future
08:17 AM vmt: well i mean there's e.g. a "picdiv" which is suitable for this, code is available for like a 50c pic
08:17 AM vmt: has a bunch of code for different divisors
08:18 AM twnqx: how much delay will you get on top, e.g. between the start of the instruction execution and the appearance of the signal on the pin
08:18 AM twnqx: simply dividing is easy
08:18 AM twnqx: precision becomes a problem
08:18 AM cehteh: slightly different, i need a PLL that generates something around 100-150khz from a not yet known but lower input
08:19 AM twnqx: that's slow
08:19 AM cehteh: with some special logic to it, it needs frequent restarts, lock in and then it gets a 'output enable' signal and shall generate 16k ticks
08:19 AM vmt: twnqx: yes, that's what i figured as well
08:20 AM vmt: i'm not sure if that's compensated for, though
08:20 AM cehteh: still brainfart stage, but the timing must be very precise i may do that on a dedicated mcu, but possibyl a fpga would be better suited
08:20 AM twnqx: fpgas have their own problems :P
08:20 AM twnqx: most are just too big
08:21 AM cehteh: yes
08:21 AM twnqx: the one i was usign last didn't have a pll (but it was cutesy small)
08:21 AM twnqx: ICE40LP384
08:21 AM cehteh: well i wnat to implement that PLL in the FPGA because its a bit special purpose
08:21 AM twnqx: i used an AVR to configure it after power up :D
08:22 AM twnqx: simple SPI slave
08:22 AM twnqx: note: wouldn't do that again)
08:23 AM cehteh: no idea how to implement it exactly when this becomes due, will see then
08:23 AM vmt: what's the lowest pin count fpgas come in and what do they go for?
08:23 AM twnqx: probably the ICE from ^ is the lowest
08:23 AM cehteh: also open source toolchain for a fpga would be nice
08:24 AM vmt: i'm on a laptop throw me a bone here, trying to copypaste with a touchpad...
08:24 AM twnqx: yeah, this one is P
08:24 AM twnqx: 1.27€ in single quantities from digikey, 32 pin QFN with exposed pad (21 I/O)
08:24 AM twnqx: but needs multiple voltages to work
08:24 AM twnqx: so everything around it makes it more annyoing (1.2V + 2.5V + 3.3V)
08:25 AM vmt: i mean if you need prescalers for multiple different frequencies then this looks pretty neat
08:25 AM vmt: buuuut unless it's brain surgery i wouldn't go the extra mile
08:25 AM vmt: for a single 10M divider
08:25 AM twnqx: i used it as a programmable 4 channel PWM controller
08:26 AM twnqx: PWM LED controller*
08:26 AM cehteh: i am completely new to FPGA's
08:26 AM twnqx: and i used a pure open source toolchain
08:26 AM twnqx: (mainly because i couldn't get the vendor one to work)
08:26 AM cehteh: lol typical :) thats my concern as well
08:28 AM twnqx: the ice40 family is pretyt well supported in open source, and i think some older spartan devices from xilinx may be
08:28 AM vmt: a few years back there was a guy who was developing a new language to replace verilog/vhdl or some interpreter for those
08:29 AM vmt: and i wonder if the project had some actual infra to it too. like a toolchain
08:29 AM twnqx: yosys?
08:29 AM twnqx: fpga dedign on a much higher level but sadly in python
08:30 AM vmt: could have been. really can't remember sadly
08:30 AM twnqx: no wait, yosys is the compiler
08:30 AM vmt: i was mildly interested in fpgas some time ago. but never got around to them
08:31 AM cehteh: i'll wait until that project becomes imminent, then i see how i do that, maybe when i am very lucky the supplier of the components firmware (linear stage) can already generate fine enough pulses
08:31 AM cehteh: i dont really expect that
08:31 AM twnqx: migen it was
08:31 AM cehteh: but worth a try
08:32 AM twnqx: migen is the high level stuff, building on yosys, nextpnr and icestorm for the ice40 series
08:32 AM vmt: probably
08:32 AM vmt: alright
08:32 AM twnqx: yosys = verilog compiler, nextpnr = place and route, icestorm = bitstream formatter
08:33 AM vmt: alright, yeah must have been this toolchain then. it was probably around 6 years ago i first read about it
08:34 AM twnqx: use it earlier this year for the first time, normally i was using xilinx' ISE (not the UI though, just the binaries ripped out via a makefile)
08:34 AM vmt: alas, something humoristic: palmer luckey's defense contractor company developed a "drone". he says they took the platform which has become a standard in the past decade, and built a new concept from first principles. guess what they came up with?
08:37 AM vmt: a single main rotor helicopter
08:37 AM vmt: rimshot. anyway carry on.
08:38 AM vmt: twnqx: i probably won't be touching fpgas anytime soon. would probably be fun to play with one, but can't think of a good application for one in a product
08:39 AM vmt: also having to learn yet another language and doing the routing and ufffff the horror
08:39 AM twnqx: yeah, they don't have that many use cases.
08:39 AM twnqx: routing?
08:40 AM vmt: what's it called? synthesis is perhaps the term?
08:40 AM twnqx: you just write the program and let the computer to the rest
08:40 AM twnqx: the rest.. sigh, germanisms
08:40 AM twnqx: anyway, you write the program, and get either an error or a ready-to-use bitstream
08:40 AM vmt: haha, alright
11:26 PM day_ is now known as day