#avr Logs

Jun 06 2020

09:08 AM rsoft: hello! having some design-related issues with the USI in a tiny2313a, specifically clock phase in SPI slave mode. the SPI master's parameters are fixed, so I can't change them. sck at 250kHz. sck idle high, data change on falling edge, data sampling on rising edge. from what I understand, that would require both clock polarity and phase to be 1, but phase is fixed at 0 for USI? I have an idea for a
09:14 AM rsoft: hacky work-around, but it's not that pretty, involving use of a counter and processing one bit manually. a completely software-based implementation wouldn't go well with my other requirements and I don't want to switch to an atmega or some other family just yet
09:14 AM twnqx: put a single chip inverter in? :P
09:14 AM twnqx: single gate*
09:14 AM rsoft: but that would only flip the polarity, not the phase, and can already be done using the configuration register
09:16 AM LeoNerd: The USI was an interesting hack to sortof do hardware-assisted bitbanging of SPI and I²C. It kindof works but it's not very fun to use
09:17 AM rsoft: do you reckon the chances of that counter-based hack for the last bit working are high enough to bother with it? (I still have to work the precise timing of that out on paper, hope the idea is obvious enough and at the same time not obviously flawed)
09:21 AM rsoft: or wait, if I idle high and have USICS0 set to 0, then the first transition to low should already advance the counter in the USI, so instead of the interrupt arriving late, it would arrive early? hm
09:23 AM rsoft: (didn't get any sleep last night, so my apologies for any scatterbrained ramblings)
09:43 AM LeoNerd: Oh to account for other phase stuff? Yeah it might work.. I did consider that myself onetime, but... given up on those chips lately instead
09:44 AM rsoft: haha, thanks
12:18 PM vmt: are we still considering joining avrs?