#avr Logs

May 04 2020

12:42 PM day_ is now known as day
02:58 PM chinry: Working on an avr project in assembly. I'm having trouble reading on my ports. Any ideas as to what may be the cause? I can send the code in a pastebin or something.
03:01 PM cehteh: write in C ... compile to asm and compare :D
03:02 PM chinry: poop
03:04 PM chinry: Idk if that would help much. I think I am just confused as to what state I should set my Ports when the data direction is set as input. Should I write the port high or low?
03:05 PM chinry: I either get 0 or 0xff
03:06 PM cehteh: when ports are set to input then the PORT data is used to drive the pullup resistors
03:06 PM cehteh: (plus some more logic alike the global pullup disable etc)
03:06 PM cehteh: thus you prolly need to read the datasheet first
03:07 PM chinry: I'll take a second look.
03:07 PM cehteh: also writing to PINx will toggle a bit in hardware in 1 instruction
03:09 PM chinry: what I am trying to do is read from an eeprom with shift registers. I am getting the correct output on the data bus so it must be the way I am reading the data.
03:09 PM cehteh: external eeprom?
03:09 PM chinry: yeah
03:09 PM cehteh: well dunno debugging is up to you, i only do asm when really required
03:10 PM cehteh: you certainly need to study the datasheet of the avr and your eeprom in detail about tming and latching characteristics
03:11 PM chinry: ok
03:29 PM Smidge204: ?
03:30 PM Smidge204: Well step one is to make sure the pin you're using is configured for input
03:31 PM Smidge204: Seems like a dumb thing to say but when doing things in ASM you can't rely on things being done implicitly
03:31 PM Smidge204: What chip is it, specifically?
03:33 PM chinry: atmega328p
03:34 PM cehteh: on boot all pins are input
03:34 PM cehteh: (or after reset)
03:35 PM Smidge204: mmkay
03:35 PM cehteh: reset resets all registers to well define states, but sram isnt altered
03:35 PM Smidge204: Correct
03:37 PM Smidge204: " If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin."
03:38 PM chinry: yeah did all of that. Here is my code https://pastebin.com/HWG9nawZ
03:39 PM chinry: line 255
03:39 PM Smidge204: lesse
03:40 PM chinry: huh?
03:42 PM Smidge204: reading
03:42 PM chinry: o
03:42 PM Smidge204: So tthe EEPROM is an SPI output?
03:43 PM Smidge204: Or is there a serial to parallel thing invovled here, hence shift register?
03:43 PM chinry: There is a shift register on spi as well as a dac
03:43 PM Smidge204: okay so the 8 bits of parallel data are attached to port D
03:43 PM Smidge204: ?
03:44 PM chinry: yeah, I am shifting out the 16 bit address to read from
03:45 PM cehteh: you jmp a lot :D
03:45 PM chinry: haha
03:45 PM Smidge204: That's ASM for you
03:45 PM chinry: I know right, lol
03:45 PM Smidge204: You're sending the address twice
03:46 PM Smidge204: Is that on purpose?
03:46 PM cehteh: you dont need to fill the isr table with jumps for unused isr's you can already place your code there
03:46 PM chinry: Yeah... I didn't feel like counting.
03:47 PM Smidge204: I usually just use an .org 0x000 RJMP start and let that be the end of it
03:47 PM cehteh: this may shadow some bugs, unexpected isr happens and jumps to timer
03:47 PM Smidge204: If none of the interrupts are enabled it will never get into it
03:47 PM cehteh: well placing code there prolly just crashes :)
03:47 PM chinry: ah
03:48 PM Smidge204: So okay, looking at read_rom_loop; You send R31 and R30 (I assume that's the 16 bit address) twice? then RCLK high which ... is that supposed to be the chip select?
03:49 PM cehteh: i'd rather make a small dead: target and jump there also in case of any error, that one just jmp dead itself, maybe flciker some diagnostic output/led
03:49 PM Smidge204: Then two NOP and set the same pin high again
03:49 PM Smidge204: For no apparentl reason
03:49 PM cehteh: eror handling is gor wussies? :)
03:50 PM Smidge204: Don'rt need error handling if your code has no errors!
03:50 PM chinry: oof
03:50 PM cehteh: :)
03:50 PM Smidge204: Anyway, you clock in the address to the EEPROM and that's fine, but if this is an SPI interface you need to also send a series of clock pulses to it can shift the data out
03:51 PM Smidge204: And I don't see that?
03:51 PM chinry: rclk is for the SN54HC595
03:51 PM chinry: clks the display flip flops
03:51 PM Smidge204: Usually it's: Clock the address (and maybe read command) in, then clock in dummy data (0x00) so it can shift the data out
03:51 PM chinry: spi is doing that
03:52 PM Smidge204: It's not, though
03:52 PM chinry: the eprom is parallel
03:52 PM Smidge204: Parallel?
03:52 PM chinry: yeah like there are 16 address pins that correspond to the 16 shift register pins
03:53 PM Smidge204: Wait wait... I'm a bit drunk so bear with me here...
03:53 PM Smidge204: The external eeprom is parallel, and you're using a shift register to load a 16-bit address into it?
03:53 PM chinry: spi has a clock that corresponds to each bit being shifted in
03:53 PM chinry: yes
03:54 PM Smidge204: ooookay
03:54 PM chinry: I can outline port C for you if that helps
03:54 PM Smidge204: So the shift register converts a serial output to a 16-bit parallel for the eeprom, and the eeprom spits out a parallel data that is direct into your MCU
03:54 PM chinry: yes
03:54 PM Smidge204: gotcha
03:55 PM Smidge204: is there no trigger to tell the eeprom that a valid address is presented on the pins?
03:55 PM Smidge204: Or a read/write line?
03:55 PM chinry: I take care of that with portc pin 5
03:56 PM chinry: thank you guys for taking a look at this mess btw.
03:56 PM Smidge204: I don't see that
03:57 PM Smidge204: I see you shift the address out (twice, but w/e), pull a line high to latch that into the shift register, then you immediately try to read in the data
03:57 PM Smidge204: I see nothing in there between the address out and data in that would tell the eeprom to read from the supplied address, assumign that's how it works
03:57 PM chinry: ohhh that's the problem then
03:58 PM Smidge204: I do see some fiddling with port c pin 5 but not where i expect it to be
03:58 PM chinry: wait so I have to re_enable the pin each time??
03:58 PM Smidge204: Problably. What eeprom chip is it?
03:59 PM chinry: m27c512
03:59 PM Smidge204: I would expect it wants a signal each time so it doesn't try to read data until the address is established
03:59 PM chinry: IDK, the datasheet is ambigous
04:00 PM chinry: *ambiguous
04:01 PM chinry: https://www.jameco.com/Jameco/Products/ProdDS/698226.pdf
04:01 PM chinry: what I found online
04:01 PM Smidge204: Right, I found the same datasheet on mouser
04:01 PM Smidge204: So chip enable (E)
04:01 PM Smidge204: And output enable (G)
04:01 PM Smidge204: Both with a line over th eletter so it's active low
04:02 PM Smidge204: (E) shold be low basically all the time if it's the only chip
04:02 PM chinry: yup
04:02 PM Smidge204: (G) shold be high until the address is loaded and stable, then once you putll (G) low, the data should appear on the output after some very small propagation delay
04:03 PM Smidge204: "Data is available at the output after a delay of tGLQV from the falling edge of G, assuming that E has been low and the addresses have been stable for at least tAVQV-tGLQV"
04:03 PM Smidge204: Emphasis mine
04:03 PM chinry: Ok I will add that to my code and I'll see what happens
04:04 PM Smidge204: Good luck!
04:04 PM chinry: Thanks for bearing with me haha
04:04 PM Smidge204: np I'm going through similar problems right now :)
04:04 PM Smidge204: (I also program entirely in ASM)
04:39 PM chinry: Yeah couldn't get it working, oh well a problem for another day.
04:56 PM Smidge204: Do you have a logic analyzer?
05:01 PM chinry: I don't but I have a Rigol DS1052D oscilloscope I am using. Do you know where I can buy a logic analyzer for one on the cheap?
05:03 PM Smidge204: Aliexpress/eBay :D
05:04 PM chinry: Cool
05:04 PM Smidge204: I only have a 1054Z so I have/use a separate LA unit
11:32 PM day_ is now known as day