#avr Logs

Apr 15 2020

12:36 PM davor_ is now known as davor
04:16 PM Smidge204_: Still learning how to use the UART... I have it triggering on an interrupt that, allegedly, should be for Receive Complete Interrupt
04:16 PM Smidge204_: But it seems to be triggering constantly
04:17 PM Smidge204_: Right now I just have it set to copy whatever comes in the RX buffer to the TX buffer, so it should just echo what I type, but it spams a character that I types two inputs ago rather than the most recent one
04:42 PM cehteh: Smidge204_: there also a TX ready interrupt, you can/should only put data into the transmit buffer when its ready for that
04:44 PM Smidge204_: WOuld that cause constant retriggering of the RXCIF?
04:44 PM Smidge204_: I'll try that but it seems unintuitive
04:48 PM Smidge204_: Didn't seem to help, I don't think the TXCIF is a factor at all.
04:49 PM Smidge204_: https://i.imgur.com/lehYadI.png Example; I type "-" twice and it starts spitting out "-" over and over without further input (first input does not cause anything change)
04:49 PM Smidge204_: I type "X" once and nothing changes, I type "X" again and it starts spamming "X"
04:50 PM Smidge204_: The only part of the code that outputs anything is inside the RXC service routine, so I have to conclude the interrupt is just being constantly triggered
04:50 PM twnqx: show us?
04:50 PM Smidge204_: It's like it's not registering me reading the data buffer
04:52 PM Smidge204_: https://pastebin.com/vnRGVm9k The meat of it
04:53 PM Smidge204_: Basically standing back from it, using LDS is not te correct way to read the input buffer, else I have to manually clear the flag which seems wrong
04:54 PM cehteh: read datasheet
04:55 PM Smidge204_: I did! Several times! :D
04:55 PM cehteh: iirc reading the data register clears the interrupt flag, at least my serial driver work pretty good
04:55 PM Smidge204_: "When interrupt-driven data reception is used, the receive complete interrupt routine must read the received data from RXDATA in order to clear the RXCIF. If not, a new interrupt will occur directly after the return from the current interrupt."
04:55 PM cehteh: but thats much more code and in C :)
04:56 PM Smidge204_: It would explain everything if the flag isn't being cleared, but LDS is the only opcode that seems to work
04:57 PM cehteh: use C :D
04:57 PM Smidge204_: Bah!
04:57 PM cehteh: well i dont know what happens when you write to the data register in the RX interrupt, never done that
04:57 PM cehteh: its the same address but reads and writes are routed differently
04:58 PM Smidge204_: RXDATA and TXDATA are different addresses
04:58 PM cehteh: what chip?
04:58 PM Smidge204_: Attiny814
04:59 PM cehteh: ah new shit, dunno that
04:59 PM cehteh: on old atmel designs its the same address
04:59 PM cehteh: can you SEI before you call dendbyte?
04:59 PM cehteh: sendbyte
04:59 PM Smidge204_: you mean CLI?
04:59 PM cehteh: dunno if that helps, i am only guessing, up to you to have fun with the datasheet
05:00 PM cehteh: ne SEI
05:00 PM Smidge204_: Global interrupts are already set
05:01 PM cehteh: iirc in isr its disabled and RETI enables it again
05:02 PM Smidge204_: I'll look into that, but I'm pretty sure some interrupts can interrupt others
05:04 PM twnqx: if you enable interrupts in your interrupt handler, yes
05:05 PM cehteh: thats because interrupts disable the global interrupt flag and reti enableds it again
05:05 PM cehteh: calling sei withing an interrupt is the hacky way to do nested interrupts
05:05 PM twnqx: https://www.mikrocontroller.net/attachment/392501/main.c that code around the interrupt handler is weird
05:06 PM cehteh: and maybe (cant remember) you even have to SEI, NOP because of the 2 instr pipeline
05:06 PM twnqx: my interpretation is that, indeed, there are other possible triggers
05:07 PM cehteh: i just done know the new-series, they have some odd/different things than the old atmels
05:08 PM cehteh: then programming those in asm sounds a bit like masochism .. esp for such non critical boiler plate stuff
05:08 PM Smidge204_: I consider myself a pioneer
05:09 PM cehteh: survival rate under pioneeers wasnt very high you know?
05:09 PM twnqx: what do you actually write to CTRLA?
05:09 PM Smidge204_: :D
05:09 PM twnqx: exact value, that os
05:09 PM twnqx: is
05:10 PM Smidge204_: 0xA0 which ought to be: RXCIE + DREIE
05:11 PM twnqx: and what does that interrupt handler look like?
05:11 PM twnqx: meh just post the full source if you don't mind
05:12 PM twnqx: (also, why three long_delay before looping... and not just sleep if you run on irqs anyway...
05:12 PM Smidge204_: laziness
05:12 PM Smidge204_: idk
05:13 PM Smidge204_: Ooooookay I think DREIE is what was doing the funni biziness
05:13 PM twnqx: >_>
05:14 PM Smidge204_: disabled that and now it's working as expected
05:14 PM * twnqx goes back to trying to fit a design into a too small fpga
05:15 PM Smidge204_: Yeah that's totally what the problem was
05:18 PM Smidge204_: Guess I have to study exactly WTF that interrupt is for. Still want to see the garbage pile of code? :p
05:19 PM twnqx: that interrupt triggers when the output reg is empty
05:20 PM twnqx: basically, you get a one byte deep queue: you write one byte to output, it is moved to shiftreg, DREI is generated, (optionally: you write another byte), the shiftreg is done clocking out, TXCIF is generated (and if you wrote another byte, that byte is loaded into shiftreg, and DREIE is generated), rinse, repeat (or don't)
05:21 PM Smidge204_: Okay fine, no idea why it would it end up in the RCX service routine?
05:21 PM Smidge204_: Or why/how it wold output the same byte over and over
05:22 PM twnqx: post your code or don't
05:22 PM twnqx: i'm not much into guessing
05:23 PM twnqx: usually, you'd use DREIE if you have a queue of data you want to send out
05:23 PM Smidge204_: https://pastebin.com/11jyGhBT main part
05:23 PM cehteh: Smidge204_: have you tried it w/o interrupts, just polling loop, reasing the same way as you send?
05:24 PM Smidge204_: https://pastebin.com/N0UCQrwP USART config + send functions
05:24 PM Smidge204_: No not yet, figured I'd shoot for the moon first
05:26 PM cehteh: lol
05:26 PM cehteh: well i have TX and RX interrupt and small queues for each
05:26 PM cehteh: with small i mean as small as 4 bytes or even less
05:27 PM Smidge204_: I've been told it's not the size of your buffer that counts but how you roll it
05:28 PM twnqx: since i never really used asm on that level
05:28 PM twnqx: did you get that initial table from some example?
05:28 PM Smidge204_: Everything is striaght from the datasheet
05:29 PM twnqx: yes, but...
05:29 PM Smidge204_: Which table?
05:29 PM twnqx: well, this is a weird 8bit arch with word addresses
05:29 PM twnqx: and i never really know when it uses "true" byte addressing, and when it uses word addresses
05:30 PM twnqx: e.g. is .org using byte addresses, or word addresses?
05:30 PM Smidge204_: Should be word since it's all part of program data space which is 16-bit
05:31 PM twnqx: all i can tell you is that inline asm in C still uses byte addresses for e.g. jmp
05:32 PM Smidge204_: This chip only supports RJMP which is 12 bit because fuck you
05:32 PM twnqx: uh.
05:33 PM twnqx: well, still enough
05:33 PM twnqx: given how little flash it has
05:33 PM Smidge204_: Exactly
05:33 PM twnqx: do you have a .elf?
05:33 PM twnqx: of your code
05:34 PM Smidge204_: no
05:35 PM twnqx: can you hexdump the binary? :P
05:35 PM Smidge204_: I have a HEX file sure
05:36 PM twnqx: pastebin the first 10 or so lines?
05:36 PM Smidge204_: https://pastebin.com/bazpA33R Here's the whole thing
05:37 PM twnqx: ah, ugly sparse hex files...
05:39 PM Smidge204_: I have an .lss file...
05:39 PM Smidge204_: 000000 c04d RJMP start
05:45 PM twnqx: anyway, you can't just IRET from DREI
05:45 PM twnqx: THAT will loop, as you either need to write data, or disable the interrupt
05:45 PM twnqx: according to the data sheet.
05:46 PM Smidge204_: I added that later just to try it, didn't work; disabled interrupt and didn't remove that bit
05:47 PM * Smidge204_ removes that before he forgets and steps on that landmine later
06:23 PM Thrashbarg_ is now known as Thrashbarg
11:47 PM day_ is now known as day