#avr Logs

Nov 03 2019

12:18 AM day__ is now known as day
08:58 AM _abc_: Apart from this crazy talk (;-) in the link from Maxim, does anyone know if multiplexing the SPI connected SD card on avr with something else, with separate SS pins works well? Example project link would be very nice. https://www.maximintegrated.com/en/design/technical-documents/app-notes/3/3947.html
08:59 AM _abc_: The SD card is a bad candidate for daisy chaining because it could be removed/missing.
08:59 AM _abc_: If one puts it at the end of the series connected chain it should work. I think.
09:00 AM polprog: ive never done spi chaining tbh
09:00 AM polprog: would be interestinf
09:00 AM polprog: interesting*
09:00 AM _abc_: Yes it would be nice to max out the speed too. Things begin to get lazy with so many things connected on a bus.
09:01 AM _abc_: I only envision 2 things for now, but both could be missing/disconnected in my case, a SD card and a SPI flash chip on a module.
09:04 AM twnqx: personally, i have a design around that uses a 3-to-8 decoder to mux SPI
09:04 AM _abc_: https://hackaday.com/2016/07/01/what-could-go-wrong-spi/ see Bad Actors
09:04 AM _abc_: twnqx: that also works but I do not have 8 devices, only 2-3
09:04 AM twnqx: so uh, spi chips that are not selected do not go tri-state?
09:05 AM _abc_: They do but some may be powered down/illegal state/just connected etc and garble the bus
09:05 AM twnqx: 'casuse then i can scrap my design before i even start and will go down the CPLD route for this :P
09:05 AM _abc_: Again, see the link
09:07 AM cehteh: _abc_: sd cards implement SPI more or less well, prolly comes down to experimenting with whatever you exactly use
09:07 AM _abc_: cehteh: per link they do not SPI mode leaves MISO dangling, no pullup transistor.
09:08 AM cehteh: i havnet read the links .. but maybe you need to add some extra stuff, often you want some transistor to power-toggle the entire card as well
09:09 AM _abc_: Right, so read the links, because they tell exactly what where and how to and when to add.
09:09 AM twnqx: interesting read
09:10 AM cehteh: well you want to do it :)
09:11 AM _abc_: I've had open circuit testing before implemented with a series resistor on the GPIO from avr or pic, turning output, and wiggling it once, checking input state immediately. A 3-state line will hold bus voltage and read what you wrote out on the gpio just before, a properly driven line holds state as set by peripheral.
09:12 AM _abc_: The series resistor prevents excessive current. I think I used 330 or 470R
09:12 AM _abc_: The problem is, this cannot be done with the SPI peripheral on on AVR, it has control of GPIOs
09:16 AM _abc_: https://www.avrfreaks.net/forum/wifi-sd-card-one-sdio-slot see last message. No multiple SD cards on same bus. But would it co-exist with other parts?
09:16 AM _abc_: Looks like I need to 3-state buffer all 4 SPI lines and ensure SS sequencing the ts buffer
09:16 AM _abc_: using only SPI mode 0
09:17 AM _abc_: The wicked part is, MISO is TS till the 1st clock pulse after SS is asserted by design. No way to tell if the card or peripheral is present till you are committed to send a code.
09:20 AM _abc_: There is no way to tell the avr spi subsystem to send one clock pulse alone.
09:20 AM _abc_: Sounds like there will be a lot of enabling/disabling the SPI peripheral then.
09:22 AM _abc_: This paper from analog.com covers all SPI modes well, including daisy chained serial. https://www.analog.com/en/analog-dialogue/articles/introduction-to-spi-interface.html#
09:23 AM _abc_: ADG1412 is a little overkill for this imo. What's wrong with 74HC4066 and or 74HC125 again? :)
09:24 AM _abc_: 1.5 ohms Ron, +/-15V capable 4066 lookalike. Le sigh.
09:25 AM twnqx: yuck, 1.5ohms
09:25 AM _abc_: Yeah, wicked parts. Overkill for SPI bus switching but I have a use for them.
09:25 AM * twnqx is annoyed at the 69mOhm his current switches have
09:25 AM _abc_: twnqx: these are analog/bus switches, not power.
09:26 AM twnqx: ah CPLD territory.
09:26 AM twnqx: if we're talking bus switches for SPI :P
09:31 AM _abc_: Another waste of parts imo
09:31 AM twnqx: nah
09:31 AM _abc_: ADG1412 is $6ish in ones
09:32 AM twnqx: i fully isolate every spi chip this way
09:32 AM twnqx: and fully mux MISO
09:32 AM twnqx: i have some of those pesky "pull MISO low to signal ready" ADC on the bus
09:33 AM _abc_: Oh yeah those suck.
09:33 AM _abc_: Also sensors on spi bus tend to do that and also some flash signals write end like that. Uhh/
09:33 AM twnqx: so i can use the cpld to generate a centralized interrupt with embedded priority encoder etc :P
09:34 AM _abc_: Iirc flash holds MISO low till write end then goes tristate
09:34 AM twnqx: hm
09:34 AM _abc_: twnqx: again, overkill.
09:34 AM twnqx: what am i supposed to do in your mind
09:34 AM twnqx: connect all miso lines via dedicated buffers to interrupt in pins?
09:35 AM twnqx: and then put in some diodes so not one going low causes all ines to go low?
09:38 AM _abc_: Just checked Micron SPI flash chip does not manhandle MISO after write, it is well behaved.
09:38 AM _abc_: Others do that, I don't remember which ones.
09:38 AM _abc_: twnqx: why interrupt? To know when they are done?
09:38 AM twnqx: yes
09:39 AM _abc_: Well that could help yes. But also consume a lot of pins
09:39 AM twnqx: that's why it's muxed in the cpld
09:40 AM twnqx: i even was contemplting an fpga that would have it's own address on the spi bus, so i would do an spi read to find the interrupt source...
09:41 AM _abc_: Oh that is overkill but whaveter you need.
09:41 AM twnqx: i like overkill.
09:41 AM _abc_: Easyest is to XOR them and create one interrupt, when you see it, you poll
09:42 AM twnqx: not THAT easy, because then a regular SPI transfer might trigger it, so you need to block off the interrupt signal from selected chips
09:43 AM _abc_: No, just ignore them on the next poll if it comes to that
09:44 AM _abc_: The xor can of course be done in a cpld beside muxing the bus. That is valid.
09:44 AM _abc_: xor edge detector, synchronous probably.
09:44 AM _abc_: Or level detector.
09:48 AM _abc_: twnqx: you can easily do it with just RS flops reset by SS going deasserted and by MISO going H (edge triggered) with R dominant.
10:01 AM twnqx: lots of effort to save 3€ on a device that you build maybe 3 of :)
10:02 AM _abc_: Oh I did not say there will be only 3 of them. And using a cpld for this is easy.
10:03 AM _abc_: EPM240 is on my to do list, has been for a while, did not get around to get the bus blaster, everything else is in place, software included.
10:04 AM twnqx: i use xilinx (exactly because i have their programmer)
10:04 AM twnqx: but yeah, it's convenient to just create arbitrary logic
10:04 AM twnqx: the lattice ice 40 fpgas are also a nice alternative, even open source software up to bitstream generation availabe, if that matters for you
10:19 AM _abc_: I use Intel's stull
10:19 AM _abc_: **ff
11:13 AM rue_bed: --
11:38 AM _abc_: ++
01:26 PM ruel is now known as lvlinux
01:51 PM nohit: --
03:07 PM djph: ÷÷
11:16 PM day__ is now known as day