#avr Logs

Apr 18 2017

05:09 AM crib- is now known as crib
05:36 AM daey_ is now known as daey
06:07 AM Jartza: wassup
06:37 AM Lambda_Aurigae: not much here.
06:37 AM Lambda_Aurigae: just getting ready for work.
06:54 AM julius: hi guys
06:55 AM julius: since my lm35 is putting out believeable data (15 degree celsius currently and im freezing my ass off) i believe the code is all good...but then someone pointed me to: The ADC Conversion Complete Interrupt is executed if the
06:55 AM julius: ADIE bit and the I-bit in SREG are set. ADIF is cleared by hardware when
06:55 AM julius: executing the corresponding interrupt handling vector. Alternatively,
06:55 AM JanC_ is now known as JanC
06:55 AM julius: ADIF is cleared by writing a logical one to the flag.
06:55 AM daey_ is now known as daey
06:56 AM julius: but im not writing a 1 to ADIF and im not using the interrupt vector for the adc....but i still get valid data..?
06:56 AM julius: this is the line of code: while(!(ADCSRA & (1<<ADIF)));
07:04 AM skz81: julius, if you don't define the corresponding vector but activate the interupt, what is executed as an ISR is the "default" one, that just reboot your chip (the assumption is that calling an "undefined" ISR is a fatal error, so just reboot)
07:05 AM julius: hm ok...
07:08 AM julius: just had to check, im not enabling the ADC interrupt
07:26 AM daey_ is now known as daey
03:38 PM polprog: yes
03:38 PM polprog: the tiny4313 board works
03:39 PM polprog: and it worked from the first avrdude try, i'm very positively surprised
03:58 PM xentrac: that's awesome! why did you doubt it?
04:24 PM polprog: mostly because my avrdude setup (cabling and stuff) tends to have terrible connectivity
04:25 PM atk is now known as ctk
04:25 PM polprog: but this time it worked awesome
04:27 PM jhn: Good evening! I have a detailed question about the tiny2/4/861: is it possible to use all six OC outputs AND SPI communication?
04:28 PM ctk is now known as edk
04:28 PM edk is now known as atk
04:29 PM jhn: MISO, MOSI and SCK share the same pins as OC1A, OC1A/, OC1B/
04:30 PM polprog: not really
04:31 PM polprog: you *could* isolate those two functions and change them on runtime
04:31 PM polprog: but thats not the best idea
04:33 PM jhn: Some avr allow remapping of MISO/MOSI/SCK to other pins, but I did not find that with the X61.
04:33 PM polprog: x61?
04:34 PM jhn: 2/4/861 = x61
04:34 PM polprog: oh
04:34 PM polprog: i never had direct experience with that serie
04:37 PM jhn: Does any of the mega have a Power stage controller, i.e. 3 pairs of complementary OC?
04:49 PM arij is now known as arij_work
04:51 PM polprog: jhn: i think theres an applet on atmels website which helps you to pick the right chip, you tell it what do you need and it shows a nice table.
04:51 PM polprog: no of my printed pinout charts seems to have 3 pairs of OC
04:53 PM jhn: yup, the tinxyx61 has for sure, the mega32m1 too, and the at90pwm series. Only I am fearing these are going away.
05:11 PM jhn: Well will read on the PWM series.
05:12 PM jhn: polprog: Thanks for your response. Good N8!
05:14 PM polprog: night, o/
05:14 PM Tom_itx: gn8
05:49 PM julius: I DID BEAT libreoffice writer, it was just crying after i was finished with it
05:50 PM julius: the end boss was called "master document" that sucker is down
08:25 PM arij_work is now known as arij
09:52 PM rue_house: ?
09:53 PM rue_house: did it try to crash on you?