Back
[14:42:25] <Lambda_Aurigae> wait! We were helpful somehow?
[14:42:30] <Lambda_Aurigae> What is this world coming to?!?!
[15:11:02] <aczid> anyone know what 'plqw' stands for in atmel product codes? something to do with the package size?
[15:12:48] <Lambda_Aurigae> which chip?
[15:13:06] <aczid> well, any
[15:13:28] <aczid> all I get is atmel chips when I google 'plqw'
[15:15:46] <aczid> seems to be an automotive thingy...
[15:17:28] <Lambda_Aurigae> 48-pin qfn package
[15:17:45] <Lambda_Aurigae> at least, everything on digikey that has that in the name is a 48-qfn
[15:18:25] <aczid> ah I didn't link it to a specific package type yet... so I guess my original hunch might have been in the right direction?
[15:18:28] <aczid> thx
[15:18:50] <Lambda_Aurigae> 1138
[15:19:12] <bss36504> If it is indeed automotive related, that is likely the qualified version of a generic package. Automotive qualification is a pain in the ass, i have first hand experience with that
[15:19:32] <aczid> ah, thanks
[15:19:39] <aczid> I think that's a satisfactory explanation for now
[15:20:00] <Lambda_Aurigae> I'm betting on the 48-qfn
[15:20:47] <aczid> I think it's both
[15:21:01] <aczid> atmel's nickname for automotive grade 48 pin qfn package
[15:22:24] <aczid> bss36504: anything in particular about automotive package qualification you'd care to vent about? :)
[15:24:32] <bss36504> Ridiculous accelerated life testing, mostly. There are different automotive grades, grade 0 to grade 3, with grade 0 being the most rigorous. I believe one of the requirements for grade 0 is 1500 temperature cycles from -40C to 180C.
[15:24:45] <bss36504> The part I was working on had failed a number of qualification cycles, so we were pushing for 2000 cycles.
[15:25:02] <aczid> wow that is amazing :D
[15:25:41] <bss36504> Which meant more work for me since every time it went through a qualification cycle there was testing before and after stress. Then you assemble drift charts to make sure individual, serialized parts don't exceed the lifetime drift spec
[15:25:41] <bss36504> And that is just one stress
[15:25:51] <aczid> i'd heard the requirements were crazy rigorous, but I'd never heard practical examples
[15:26:13] <bss36504> You also need to run three separate wafer lots through qual in order to truly be "qualified".
[15:26:34] <aczid> sounds expensive
[15:26:51] <bss36504> One of my coworkers had a part with three dies in the same package, and about 150 different spec tests to run. So his drift reports were like 600 pages long lol
[15:27:33] <bss36504> It is, for us it was about 20K per group, so if all goes well its 60K NRE for each part we release
[15:27:38] <aczid> I'm sorry I'm a noob, what is drift in this sense? performance degradation?
[15:27:51] <bss36504> my poor part went through roughly 12 Qual cycles lol
[15:28:00] <bss36504> not my fault that the die was cracking in half during temp cycle
[15:29:20] <bss36504> drift is basically how much does the performance change over the life of the part. This was a current sensor, so we spec sensitivity as 13.3mv/A nominally, with 1% accuracy at 25C. Then after stress it needed to be within 3.25% I believe.
[15:29:36] <aczid> gotcha
[15:29:39] <bss36504> the specs on the datasheet say "Accuracy 1%, lifetime drift 3.25% max
[15:29:39] <bss36504> "
[15:30:20] <bss36504> I don't do that job anymore, too much paperwork and meetings haha
[15:32:06] <aczid> still, sounds interesting when not doing that part
[15:32:53] <bss36504> Yeah it had it's interesting parts. I enjoy optimizing things, so I had a lot of time for test time reduction work since the release was delayed by qual cycles
[15:33:16] <bss36504> I inherited a test program from a former employee and cut the test time by over 70%
[15:33:58] <bss36504> Also did some work with our equipment group to improve the consistency between the different contact sites in the part handler
[15:46:29] <aczid> the part as in the package or as in the die?
[15:46:41] <aczid> the wafer*
[15:47:12] <aczid> not sure what the correct terminology is here
[15:47:45] <aczid> I assume the dies have to be handled when packaged too
[15:48:29] <bss36504> package and die actually. There was a certain geometry that caused a micro-fracture in the package which traveled right up through the die.
[15:48:44] <bss36504> The die is the single chip, cut from the wafer
[15:50:08] <aczid> so is this packaging work something that happens at a fab?
[15:50:36] <aczid> do they ship pre cut dies to you or do you get wafers delivered
[15:50:55] <bss36504> We designed the package in house, then have the assembly house dice the wafers and assemble the finished parts. The parts worked great, right up until you temp cycle it.
[15:51:24] <bss36504> The root cause of the problem is that the packaging engineer is an idiot who didn't think
[15:51:31] <aczid> i see :)
[15:51:40] <aczid> engineers... always goofing off
[15:52:25] <bss36504> The package is called a "flip chip" package because the die is actually flipped over (like contacts down) and soldered to the leadframe, similar to how a BGA goes on a PCB. This is contrary to wirebonding the pads to the leadframe.
[15:53:11] <aczid> pretty much everything I know about microchip fabrication is from a talk called "indistinguishable from magic" that was given at HOPE con a few years ago
[15:53:25] <bss36504> Now, when you take a piece of what is basically glass and rigidly affix it to two dissimilarly sized hunks of metal and then heat and cool it a bunch of times, stuff is going to move around, and in this case, break
[15:54:01] <aczid> so is this design easier/cheaper than wire bonding?
[15:54:31] <bss36504> The assembly portion is pretty straightforward, it's similar to PCB stuff, just on a much smaller scale. The wafer build process gets kind of funky, especially at very small technology nodes, like sub-14nm
[15:54:47] <aczid> yeah, very crazy as I gathered from that conf video
[15:55:07] <bss36504> I believe it was slightly cheaper, but it also allowed for a smaller package relative to the die size, since we didnt need room around the die between it and the leadframe.
[15:55:11] <aczid> printing features smaller than the ultra UV light used to print them o_O
[15:55:26] <bss36504> Also this necessitated having leadframe directly under the die
[15:55:40] <bss36504> multiple patterning and extreme UV is really complex
[15:55:43] <aczid> so very small footprint
[15:55:46] <aczid> ?
[15:56:02] <aczid> nice :)
[15:56:16] <aczid> also I heard something about submersion lithography
[15:56:17] <bss36504> the machine used to generate the EUV is literally a molten tin dripping into a laser, where it gets turned into a plasma. Its fucking insane
[15:56:27] <aczid> :D
[15:56:50] <Lambda_Aurigae> laser soldering!
[16:03:56] <Jartza> evening
[16:04:02] <Jartza> wassup?
[16:05:32] <bss36504> Oh not much, we were just discussing the woes of automotive qualification and that led into semiconductor fabrication
[16:07:22] <Jartza> mkay
[16:08:08] <bss36504> sup with you?
[16:19:58] <Jartza> not much
[16:20:15] <Jartza> continued the long-forgotten project of writing blog about my stupid attiny85 vga :D
[16:31:10] <Jartza> maybe one day :)
[17:16:06] <Lambda_Aurigae> is not stupid.
[17:16:11] <Lambda_Aurigae> is actually useful!
[17:18:18] <Lambda_Aurigae> Jartza, didn't you do an attiny13 vga too?
[17:18:28] <Lambda_Aurigae> hackaday is having a 1K contest.
[17:38:38] <Jartza> Lambda_Aurigae: oh no. I did attiny5 :D
[17:38:43] <Jartza> the 6 pin chip
[17:38:54] <Jartza> with 512 bytes flash & 32 bytes ram
[17:38:58] <Jartza> 8 colors
[17:39:00] <Jartza> :P
[17:39:24] <Jartza> https://www.youtube.com/watch?v=qucJMObCUpI
[17:39:28] <Jartza> nothing too impressive, though
[17:39:51] <Lambda_Aurigae> that would qualify.
[17:39:59] <Jartza> https://www.youtube.com/watch?v=swg2WneeWgU
[17:40:04] <Jartza> there's another
[17:40:14] <Jartza> although neither is not even close to 512 bytes
[17:40:15] <Jartza> :D
[17:41:12] <Jartza> octapentaveega code is 1624 bytes, rest is font
[17:41:29] <Lambda_Aurigae> yeah...that's over the 1K limit
[17:43:21] <Jartza> yeps
[17:46:45] <Jartza> but sure something fun could be done
[17:47:25] <Jartza> Lambda_Aurigae: is there a link to the competition?
[17:48:00] <Lambda_Aurigae> http://hackaday.com/2016/11/21/step-up-to-the-1-kb-challenge/
[17:48:14] <Lambda_Aurigae> https://hackaday.io/contest/18215-the-1kb-challenge
[17:48:49] <Jartza> thx
[17:49:33] <Lambda_Aurigae> 1138
[18:06:57] <Jartza> I dunno. Maybe some kind of game with attiny85
[18:07:01] <Jartza> I have lot of them still
[18:07:22] <Lambda_Aurigae> I have a couple of them playing displays for little projects here.
[18:07:57] <Lambda_Aurigae> one is a weather station in progress and the other is a home automation controller unit.
[18:08:39] <Jartza> or maybe I try out the new attinies
[18:08:41] <Jartza> like 817
[18:08:46] <Jartza> pretty awesome chips they are
[18:09:11] <Jartza> seems microchip brought some amazing stuff to avrs :)
[18:09:46] <Lambda_Aurigae> no dippy package though.
[18:10:24] <Lambda_Aurigae> cap sense channels rock though.
[18:11:11] <Lambda_Aurigae> added a dac too.
[18:13:23] <Jartza> did you look at attiny817?
[18:13:34] <Jartza> it's pretty awesome... I don't know why they call it "tiny"
[18:13:48] <Jartza> it's like... xtiny
[18:14:10] <Lambda_Aurigae> looking now.
[18:14:39] <Jartza> the core even has MUL
[18:14:52] <Jartza> which previously was like "the line between" tiny and mega
[18:15:17] <Lambda_Aurigae> virtual ports?
[18:15:45] <Jartza> memory mapped flash, spi, i2c and uart
[18:18:01] <Jartza> two 16 bit timers, 1-chan 8 bit d/a, 12-chan 10 bit a/d, picopower (1.8V), new power saving modes, sleepwalking, 12 bit timer for waveform generation...
[18:19:21] <Jartza> oh and i2c supports fast mode plus (1Mhz)
[18:20:03] <Jartza> yea. really "tiny"
[18:20:10] <Jartza> costs about 0.5€
[18:20:35] <Jartza> oh... this I didn't notice before:
[18:20:36] <Jartza> Configurable Custom Logic (CCL) with Two Programmable Lookup Tables (LUT)
[18:20:52] <Lambda_Aurigae> new programming interface too.
[18:21:03] <Jartza> yea. and debug interface.
[18:21:31] <Jartza> Gated D Flip-Flop, JK Flip-Flop, gated D Latch, RS Latch
[18:21:35] <Jartza> oh... cooool
[18:22:15] <Jartza> pretty amazing chips I'd say
[18:23:04] <Lambda_Aurigae> seems the programming interface is documented.
[18:24:00] <Jartza> yep
[18:26:14] <Jartza> that CCL seems pretty cool
[18:27:34] <Lambda_Aurigae> yeah
[18:27:42] <Lambda_Aurigae> I have a couple of pic chips with that in it.
[18:27:57] <Lambda_Aurigae> haven't found an actual use for it yet though.
[18:29:19] <Jartza> I bet some of the peripherals are taken from microchip
[18:29:26] <Lambda_Aurigae> yes.
[18:29:28] <Lambda_Aurigae> they are.
[18:29:34] <Lambda_Aurigae> I've seen them in pic chips.
[18:30:45] <Jartza> and yeah. also bootloader section in this tiny
[18:32:44] <Lambda_Aurigae> hardware multiplier?
[18:32:48] <Jartza> The Event System (EVSYS) enables direct peripheral-to-peripheral signaling. It allows a change in one
[18:32:52] <Jartza> peripheral (the Event Generator) to trigger actions in other peripherals (the Event Users) through Event
[18:32:55] <Jartza> channels, without using the CPU.
[18:32:56] <Jartza> Lambda_Aurigae: yes
[18:33:06] <Lambda_Aurigae> hmm.
[18:33:15] <Lambda_Aurigae> it would be awesome to have this setup in an atmega.
[18:33:22] <Lambda_Aurigae> like an upgraded atmega1284p
[18:33:29] <Jartza> I've heard rumors new atmegas are coming too
[18:33:39] <Lambda_Aurigae> yup.
[18:33:46] <Jartza> if tinies are getting this awesome already, I can't wait the atmegas
[18:33:49] <Lambda_Aurigae> that evsys is like a dma-light.
[18:33:53] <Jartza> would give them some more years of lifetime
[18:34:52] <Lambda_Aurigae> 100MHz with internal PLL would be awesome.
[18:35:04] <Jartza> sure
[18:35:38] <Jartza> but still lot of awesome features that have been norm for arm chips for a long time
[18:35:47] <Lambda_Aurigae> yup
[18:35:56] <Lambda_Aurigae> PPS will be nice.
[18:36:09] <Jartza> PPS?
[18:36:17] <Lambda_Aurigae> peripheral pin select
[18:36:27] <Jartza> ah
[18:36:29] <Lambda_Aurigae> moving peripherals to other pins.
[18:36:34] <Jartza> yea
[18:36:40] <Lambda_Aurigae> pic has it on some chips.
[18:36:45] <Lambda_Aurigae> lots of arm chips do too.
[18:37:01] <Jartza> yeah. I think many arm chips call it pinmux
[18:39:32] <Lambda_Aurigae> the virtual ports look like a first step toward PPS on avr.
[18:39:44] <Lambda_Aurigae> I need to read the whole datasheet.
[18:42:07] <Jartza> yep. I'm reading it too.
[18:42:17] <Jartza> looks like a chip I wanna test
[18:44:51] <Jartza> timers/counters look totally different from other tinies
[18:44:59] <Jartza> even register and bit names are totally different
[18:46:44] <Jartza> Lambda_Aurigae: ps. I made a fun test-version of octapentaveega, displaying 32x18 characters :)
[18:46:49] <Jartza> but it's bugging a bit
[18:47:07] <Jartza> that's 576 characters in 512 bytes of ram :)
[18:47:42] <Lambda_Aurigae> oops
[18:48:09] <Jartza> yea
[18:48:19] <Jartza> but my timings are bugging
[18:48:31] <Jartza> that's pretty pretty cycle deprived code now
[18:49:01] <Jartza> it's using 7 bytes to draw 8 characters :)
[18:49:11] <Jartza> downside: no reverse text now
[18:49:26] <Jartza> and I haven't even thought about the 8-color version with that :)
[18:49:32] <Jartza> just wanted to see if it can be pushed even more
[18:50:26] <Jartza> so actually it's only using 504 bytes of display ram
[18:57:09] <Jartza> anyway... gonna hit the sack for today :)
[18:57:11] <Jartza> g'night!
[18:59:27] <Lambda_Aurigae> laters