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[07:56:46] <Chocobo> Hi all. I have noticed several placed (xboot included) where the DFLL is enabled without setting up, or starting the reference source. That is not correct is it?
[08:38:00] <rue_school> dfll?
[10:55:45] <fruitalert> Hi, does anyone have experience using LUFA on a at90usb162 and could tell me how many cycles the USB ISRs take max?
[11:01:37] <fruitalert> I wish to have the µC control a controllerless display that needs constant refreshing, and fear that it might flicker when USB activity takes place.
[12:24:27] <Chocobo> In osc_enable_autocalibration() can anyone tell me why Atmel enables the internal 32KHz clock if the DFLL reference is the external oscillator??
http://spaces.atmel.com/gf/project/asf/scmgit/?p=asf;a=blob_plain;f=common/services/clock/xmega/osc.h
[12:24:43] <Chocobo> It is about 3/4 of the way down the page.
[12:45:55] <Chocobo> Nevermind, it appears to be a bug:
http://asf.atmel.com/bugzilla/show_bug.cgi?id=3455
[14:17:47] <phinxy> in this assembler emulator theres a orange highlight at the bottom. is this the stack? Why does it get larger without any data in it?
http://schweigi.github.io/assembler-simulator/
[15:34:46] <dmitescu> Has anyone here used autotools for personal avr projects?
[15:37:15] <Yoduza> avr-gcc ?
[15:38:43] <dmitescu> Autotools.
[15:38:51] <dmitescu> autoconf, autoreconf, etc.
[15:43:53] <phinxy> what happens if theres a memory leak and you get a too big stack for example
[15:56:46] <Jartza> I've used autotools, but never for avr project
[16:10:12] <day> i need some help. im trying to read this rs232 signal.
http://i.imgur.com/YEIbSE0.png. It is a bit weird because it idles low, but is not inverted. My idea was to clear the UDR register when the signal goes to high. basically hiding the weird 'low idle' from the receiver.
[16:11:16] <day> the strange part is that i then wait till the RXD flag is set, then read UDR and that process 14times. But the loop exists almost instantly. which seems weird
[16:12:15] <day> to make sure the loop actually is working, i toggled and _delay_us(100) a pin (channel 7 on the pic) which works just fine
[16:19:41] <day> here the example what happens when i try to read the bytes + Channel7 toggle infront and behind each byte
http://i.imgur.com/ZK5Gczv.png http://dpaste.com/12F80C5
[16:19:48] <day> this doesnt make sense
[16:20:35] <day> channel 7 toggles @1.7Mhz and the USART is running at 4800Baud :D
[16:22:38] <day> the wait loop is finished and therefore the RXD register filled after 0.25uS which obviously is impossible
[17:07:59] <dekeneus> Ah screw this. Are the atxmega128a1u header files compatible with a4u?
[17:08:22] <dekeneus> There are no a4u header files... None which I can seem to find.
[17:13:20] <rue_school> I just use a straight makeifle
[17:15:07] <rue_school> day, isn't there a flag that determines if the uart goes into ... oh whats it called, standby or idle, something like that
[17:15:27] <rue_school> one of them goes high when idle and one of them goes low
[17:19:32] <day> rue_school: not sure what you mean. you mean the 'rxc' interrupt flag? that is set when something is received?
[17:20:18] <rue_school> no, a serial line idling high as opposed to low means something
[17:20:23] <rue_school> so you should be able to control it
[17:20:34] <rue_school> I forgot the meaning of the two levels
[17:21:00] <rue_school> pretty sure one of them means "wait I'm gonna send more" and the other means "I'm done"
[17:21:01] <day> rue_school: high idle is standard
[17:21:17] <day> there is nothing like that
[17:21:24] <rue_school> its lost meaning with modern use of serial
[17:21:40] <day> there is a dedicated wire for that
[17:21:47] <rue_school> I bet if I dig thru a 8250 datasheet I can find it
[17:22:08] <day> you mean flow control?
[17:22:18] <rue_school> nope, its something really legacy
[17:22:31] <day> why did you bring it up?
[17:25:56] <rue_school> I'm looking for hte name of the flag your obviously looking for
[17:27:03] <day> im not sure why that flag would matter in my case :/
[17:27:57] <day> the avr example does two things: "setup the protocol parameter 8bits, stopbits, baudrate etc." wait till UDR is filled, read UDR done
[17:30:03] <day> the only thing that is abit special in my case is, ive connected another pin to the RX pin. so its like this: TXD -> RXD (uC) && INT0 (uC)
[17:30:42] <rue_school> break/space
[17:31:30] <rue_school> so, when the trnasmitt is finished, does it go to break or space
[17:33:53] <day> The RXD read complete flag is set instantly.
[17:34:06] <day> thats why my loop finishes instantly
[17:34:39] <rue_school> I thought your challange was to transmitt with the opposite of a normal idle state
[17:37:04] <day> nono the signal im receiving is a bit twisted. thats it. with the INT0 interrupt i show the usart interface a perfectly normal non inverted 7bit + 1 stop bit signal
[17:37:07] <rue_school> oh, no provision for sending a break on the avrs, that sucks
[17:37:37] <day> http://i.imgur.com/kRdFQMR.png
[17:37:45] <day> the five blocks are what im interested in
[17:38:04] <rue_school> with breaks in between I suppose they are
[17:38:07] <rue_school> instead of spaces
[17:38:08] <day> so im locating the long delays with INT0 + timer
[17:38:29] <rue_school> surprised the uart cant detect breaks
[17:39:06] <rue_school> I'm going to go write a program to make school problems so i can solve thm by hand
[17:39:10] <day> it doesnt see them because im clearing UDR when the signal starts to look normal ;)
[17:39:29] <day> at the beginning of the small blocks
[17:42:44] <day> OMG. i got it. i had to clear UDR twice :D
[19:08:46] <rue_school> geez, so many emergency vehicles go by here, they should have a dedicated lane
