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[02:00:29] <Jartza> yea
[02:01:19] <Jartza> seems that when using USICLK bit to clock the USI, sometimes it takes more than 1 clock cycle to complete. depends of the data.
[02:02:00] <Jartza> which is baffling, as "sbi 0x0d, 1" is one opcode which should finish in 1 clock cycle
[02:10:58] <Jartza> oh. seems to only happen when running at 20MHz
[02:11:04] <Jartza> 16MHz does fine
[02:18:28] <Jartza> hmm. maybe my 20MHz clock wasn't stable then?
[02:19:55] <Casper> that can be possible, specially on breadboard
[02:20:30] <Jartza> yep
[02:21:07] <Jartza> it was just strange that sending 26 times byte 0xAA, it took ~28us, but if I sent 0 or 255, it ran in ~23us
[02:22:20] <Jartza> like this:
http://pastie.org/10272600
[02:22:47] <Jartza> exactly the same code (and exactly the same assembler, except the value 170 / 255) but different runtime
[02:24:18] <Jartza> but using value 255, it ran slower
[03:02:02] <Xark> Jartza: Is this with software SPI (or similar)?
[03:02:27] <Xark> No, USI...that is odd.
[03:03:05] <Xark> Jartza: I haven't see that in the USI stuff I've done (examined with logic analyzer, e.g.).
[03:38:42] <Jartza> Xark: me neither. with 16MHz it works just as it should
[03:38:53] <Jartza> but when I change the oscillator to 20MHz, it starts to fail
[03:39:05] <Jartza> vcc is 5V so it's not even that
[03:39:18] <Jartza> I know 20MHz fails with <4.5V sometimes
[03:40:41] <Xark> Jartza: That is odd. I am ran my ATTiny at 20Mhz (needed to to get speed up to match 328P HW SPI [actually was a tad faster]). ->
https://imgur.com/WKg33E7 (not latest benchmark pictured).
[03:40:50] <Xark> am pretty sure^
[03:41:30] <Xark> I was 3.3v (but probably out of spec - for 328 also).
[03:43:46] <Jartza> yeah
[03:43:48] <Jartza> this is very odd
[03:43:52] <Jartza> only happens with 20MHz
[03:44:06] <Jartza> but might be that my caps for oscillator are off for 20Mhz when using breadboard
[03:44:19] <Jartza> maybe I try soldering the osc directly to MCU pins :)
[03:46:06] <Xark> Ahh, I was using internal RC (with PLL for 20MHz).,
[04:00:41] <Jartza> well
[04:00:46] <Jartza> I'm misusing USI anyway :)
[04:01:04] <Jartza> I'm pretty sure I can get 30x14 character output to VGA from attiny85 :D
[04:11:33] <Jartza> ahh
[04:11:40] <Jartza> seems it was unstable clock
[04:12:15] <Xark> Okay, that does make some sense.
[04:12:17] <Jartza> changed the caps
[04:12:22] <Jartza> and now it works like it should
[04:15:00] <Jartza> switched the 22pF caps to 6pF :P
[04:15:10] <Jartza> but these are veryveryvery-el-cheapo-crappy caps anyway
[04:15:22] <Jartza> and breadboard adds its own capacitance anyway
[04:17:07] <Jartza> funny thing was that everything else was ticking nicely @20MHz, the problem only showed when using USI :)
[04:19:42] <Jartza> I had to check with oscilloscope and yes, with the 22pF caps the output started acting funny
[04:20:08] <Jartza> with 15pF caps it acted less funny, but still it wasn't serious enough :D
[04:20:17] <Jartza> 6pF seems to be ok. maybe this is just crappy breadboard too.
[04:20:35] <Xark> Yeah. Probably should double check xtal datasheet.
[04:20:48] <Xark> BB will add some capacitance.
[04:21:19] <Xark> I think I have some xtals that want 19pF (IIRC).
[04:44:01] <Jartza> ha
[04:44:18] <Jartza> outputting 36 * 5 pixels with usi, 23.6us
[04:44:38] <Jartza> fits well within 25.4us that's vga visible line ;)
[04:44:55] <Xark> Jartza: Cool, so doing VGA with ATTiny?
[04:45:00] <Jartza> yea
[04:45:04] <Jartza> thought to misuse USI for it
[04:45:14] <Jartza> specifically attiny85
[04:45:24] <Jartza> one color only, though
[04:45:30] <Xark> Neat. I have only done NTSC with AVR (but I did do some 8051 VGA). :)
[04:45:32] <Jartza> I would like to get 36*12 characters
[04:45:53] <Jartza> so, no graphics, just text mode
[04:46:24] <Jartza> and filling the USI data register automatically creates space between characters, so I can use 5*8 font
[04:46:28] <Jartza> or 5*7, whatnot
[04:46:33] <Xark> links AVR NTSC
https://www.youtube.com/watch?v=Imk5ony8JHI and
https://imgur.com/a/JO4Cq and 8051 VGA
https://imgur.com/a/Jtr2C#2
[04:46:39] <Jartza> cool
[04:47:07] <Jartza> I know there are lot of vga solutions for avr too
[04:47:13] <Xark> I think my VGA was 160x128 or so (with blank scans to calculate next line).
[04:47:34] <Jartza> but as a friend of mine once said, "I think everybody should write their own CRTC once"
[04:47:58] <Xark> Yeah. FPGAs are much better at VGA though. :)
[04:48:09] <Jartza> of course
[04:48:24] <Jartza> lot of people already have suggested "why not use xmega, why not use cortex m, why not use fpga?"
[04:48:28] <Jartza> but it's not the point
[04:48:31] <Xark> The sprite stuff was a bit tricky to get right (but works pretty good with 2K SRAM). :)
[04:48:32] <Jartza> point is minimalism :)
[04:48:56] <Jartza> 512B sram and 8 pins gives some challenges
[04:49:15] <Xark> ~22x22 8x8 tiles, with 128 tiles in flash, and 128 in SRAM (leaving ~.5KB free for your "game"). :)
[04:49:18] <Jartza> where external osc eats 2 pins, leaving 3 usable :)
[04:49:41] <Xark> Yeah. I experimented with RC but not good enough for decent video.
[04:50:04] <Jartza> Xark: cool. I'm planning to include one pin for uart, so this could be used as "external graphics card" :D
[04:50:17] <Jartza> or more likely, external "text video card"
[04:50:50] * Xark stalled on his game once the "tech" worked https://imgur.com/IgsmEY3 and https://imgur.com/gNyTb6u (has horizontal and vertical smooth scrolling too).
[04:51:54] <Xark> Can you reliably read UART with video out?
[04:52:17] <Xark> Sounds tricky...
[04:52:28] <Xark> (without serial hardware at least)
[04:53:02] <Xark> I was able to read/write 19.2Kbps but on 328P (checking UART buffer once per scanline)
[04:54:18] * Xark bit-banged his video (4 clocks per pixel - other than 40 column @ ~2clocks per pixel).
[04:54:48] <Xark> NTSC is a lot easier timing-wise, of course.
[05:02:12] <Jartza> Xark: I'm aiming somewhere between 2400-9600bps
[05:02:22] <Jartza> not sure if I can read it "reliably" but I'll try :)
[05:02:38] <Jartza> first I want to get this picture to stabilize, some timing issues still
[05:06:10] <Xark> Yeah, first things first. :)
[06:35:11] <Jartza> almost
[06:38:52] <Jartza> https://drive.google.com/file/d/0B2dTzW9TMeBxRWtYbS0weU1pSnM/view?usp=sharing
[06:39:04] <Jartza> (tried getting vertical bars)
[06:46:33] <Xark> Hmm, uneven timing, or LCD monitor "quantizing" odd horizontal rez?
[06:46:48] <Jartza> yeah, some timing issues still
[06:46:56] <Jartza> but at least I can sometimes see the vertical bars :D
[06:47:01] <Xark> :)
[06:47:29] <LeoNerd> Definitely progress
[06:47:35] <Xark> Indeed
[06:49:10] <Jartza> the vertical bars still show that my USI-thingamabob works
[06:51:38] <Xark> Jartza: I wonder if you are getting an unwanted "9th bit" (normal AVR SPI does this, but not sure about USI).
[06:52:13] <Jartza> nope
[06:52:28] <Jartza> but I get blank pixels when pushing new value to USI buffer
[06:52:48] <Jartza> which is OK as I want text, it makes blank between letters "automatically" :)
[06:53:08] <Xark> :)
[06:53:30] <Xark> How many "cycles per pixel"?
[06:53:38] <Xark> 2?
[06:53:58] <Jartza> 1
[06:54:06] <Jartza> just one sbi
[06:54:21] <Xark> Okay, that is 2 cycles, I think.
[06:54:28] <Jartza> oh, indeed
[06:54:45] <Jartza> yeah. running @20MHz, pixels outputted @10Mhz
[07:06:14] <Jartza> hmm. vsync is 59.91Hz, so it must be hsync prob I guess
[07:06:47] <Jartza> oh yeah
[07:06:50] <Jartza> it's off
[07:07:46] <Jartza> well, I guess, off too much
[07:19:15] <Jartza> ahh. closer
[07:22:49] <Jartza> https://drive.google.com/file/d/0B2dTzW9TMeBxU19jMW1JakN0SlE/view?usp=sharing
[07:22:53] <Jartza> at least I think it's closer :)
[08:14:37] <Lambda_Aurigae> Jartza, I have an old nec multisync LCD and an even older nec multisync tube monitor.
[08:14:55] <Lambda_Aurigae> I use those when doing vga testing because they are a lot more forgiving
[08:16:08] <Jartza> yea, that would be cool
[08:16:10] <Jartza> but I don't have one
[08:17:31] <Lambda_Aurigae> the tube one can do old mono, ega, cga, vga, and svga up to 1024x768
[08:18:07] <Lambda_Aurigae> I'm betting it can even do the old half-res vga too.
[08:21:35] <Jartza> ohh
[08:21:45] <Jartza> I do need to generate hsync signals during vsync too?
[08:22:39] <Lambda_Aurigae> umm...depends on the monitor, but, yeah, I do.
[08:23:28] <Lambda_Aurigae> I really need to dig that board back out and work on that project some more.
[08:23:45] <Lambda_Aurigae> just been so busy doing house stuff and enjoying my summer days off relaxing as much as possible.
[08:23:50] <Jartza> then it might be that I need to generate vsync differently
[08:25:09] <Lambda_Aurigae> http://www.javiervalcarce.eu/html/vga-signal-format-timming-specs-en.html
[08:26:08] <Lambda_Aurigae> hmm..I guess the hsync doesn't need to be generated during vsync as your horizontal would be totally off during that time.
[08:27:23] <Lambda_Aurigae> on mine, hsync runs constantly and is used to trigger a couple of different pieces.
[08:27:25] <inflex> Anyone got a 22-pin SATA PCB plug/socket pad layout for Eagle? I can do one up, but damn, moderate amount of work
[08:27:47] <Lambda_Aurigae> inflex, sorry, not here..
[08:28:08] <Lambda_Aurigae> that's waaaay above hobby level gear and I don't touch that kinda stuff as a general rule.
[08:31:04] <inflex> ja, findig that almost none seem to be around. All I'm doing is adding a power rails switching facility
[08:34:02] <inflex> Ah, con-tyco has one
[09:34:46] <Jartza> hmmh
[09:35:01] <Jartza> my timing must be very close, but no cihar
[09:35:04] <Jartza> cigar
[09:35:55] <Jartza> maybe I need to try first without isr
[09:36:36] <Jartza> it's harf to get exact timing with 8-bit timers
[09:37:04] <Jartza> and even harfer to type with this touch-kbd, it seems :D
[09:37:16] <Jartza> but first some food
[09:41:53] <megal0maniac> Anyone ever done I2C with an xmega?
[11:10:18] <Lambda_Aurigae> megal0maniac, I'm sure someone has.
[11:10:25] <Lambda_Aurigae> not I as I've never had an xmega.
[12:14:28] <megal0maniac> Lambda_Aurigae: I'm not convinced that anyone has ever had an xmega, actually
[12:14:42] <Lambda_Aurigae> me neither
[12:14:46] <Lambda_Aurigae> but it's a good theory.
[12:14:56] <Lambda_Aurigae> I have wanted one but just didn't see a need really.
[12:15:14] <Lambda_Aurigae> and soldering a SMT package chip just isn't something I want to fuck with lately.
[12:16:33] <Lambda_Aurigae> specially when I can get similar performance from a 28pin dip package pic32 chip.
[12:21:56] <megal0maniac> I'm not a fan of PIC in general, although I do have quite a selection of them. I got the xmegas as samples and breakouts from ebay. Soldering is easy on the 32pin variants
[12:24:52] <Lambda_Aurigae> I'm not a pic fan either but the pic32 is not a pic core..it's a mips core with pic peripherals...and pic has some peripherals that avr doesn't..
[12:25:01] <Lambda_Aurigae> AND, I can get a pic in dip package that has usb hardware.
[12:25:54] <Lambda_Aurigae> a 28 pin dip package with 256K flash and 32K sram, 32bit processor, usb-otg(with host and device modes), and 50MHz/80dmips
[12:26:17] <Lambda_Aurigae> oops...64K sram
[12:26:23] <Lambda_Aurigae> 32K was the previous model.
[12:26:44] <Lambda_Aurigae> so, comparable to an xmega really.
[12:27:23] <Lambda_Aurigae> this chip is proving fun for building a retro-ish computer system as I can put the kernel in flash and have 64K of sram that I can use for both user programs and data.
[12:27:30] <Lambda_Aurigae> as it can actually execute code from sram.
[12:28:10] <megal0maniac> Hmmm... Maybe I should look at using that chip instead
[12:28:15] <megal0maniac> I think I have some
[12:28:30] <Lambda_Aurigae> trying to devise a compiler that will reside in flash and can compile to native code.
[12:28:37] <Lambda_Aurigae> pic32mx270f256b
[12:28:52] <Lambda_Aurigae> not a lot of hardware i/o but lots of stuff packed into the package.
[12:29:27] <megal0maniac> PIC32MX250F128B
[12:29:34] <Lambda_Aurigae> including dual spi, dual i2c, usb full speed device/host/otg
[12:29:37] <megal0maniac> I guess that's the previous one
[12:29:38] <Lambda_Aurigae> that's the little brother.
[12:29:44] <megal0maniac> Cool. I have like 10
[12:29:45] <Lambda_Aurigae> 128k flash and 32k sram.
[12:29:50] <Lambda_Aurigae> otherwise the same chip basically.
[12:30:46] <megal0maniac> I need it to read an I2C temp sensor or 3, communicate over serial at 115200 using a plaintext protocol without falling behind, and operate at 3v3. And be easy enough to program, of course
[12:31:21] <Lambda_Aurigae> mplabx is available multiplatform...along with xc32 compiler.
[12:32:34] <Lambda_Aurigae> I used the one you have to generate 800x600 vga at 200x150 resolution a while back and using internal sram for graphic buffer.
[12:32:54] <Lambda_Aurigae> it was mono-vga.
[12:32:59] <Lambda_Aurigae> but was readable.
[12:33:28] <Lambda_Aurigae> it has 2 uart and 2 i2c modules...the uart modules can do regular rs232 type or spi.
[12:34:08] <megal0maniac> I'll check it out. If it's easy enough to do what I want, then I might go for it
[15:12:00] <tis_me> I'm starting with USI on an ATtiny85 and am confused about what will toggle the USCK pin when using USICS 00 or 01.
[15:12:28] <tis_me> Does it toggle with the counter, the USIDR, or neither?
[15:15:19] <Lambda_Aurigae> kinda depends on what mode you are running it in.
[15:15:21] <Jartza> d'oh
[15:15:25] <Jartza> very close the timings must be
[15:15:40] <Lambda_Aurigae> Jartza, yes...very very close.
[15:15:44] <Lambda_Aurigae> if you are talking about vga.
[15:15:50] <Jartza> yeah
[15:16:00] <Jartza> now the pic shows for like 3-5 secs
[15:16:10] <Jartza> and then goes black and syncs again
[15:16:23] <Jartza> also there's no more jitter on vertical lines
[15:16:32] <Jartza> but something I might not get
[15:45:36] <Xark> Lambda_Aurigae: I think RetroBSD has a small compiler that can run native ->
http://retrobsd.org/wiki/doku.php :)
[16:28:03] <LeoNerd> tis_me: You have to toggle the pin yourself
[16:42:46] <Jartza> arrrrh
[16:42:48] <Jartza> https://drive.google.com/file/d/0B2dTzW9TMeBxamttU1ViaVp2MHM/edit?usp=docslist_api
[16:43:36] <Jartza> I've checked with saleae the signals and I think they should be correct
[16:43:46] <Jartza> but seems they're not
[16:43:54] <Xark> Yeah, as I understand it, you set it to initial value and then each write to SCK will toggle it.
[16:44:06] <Jartza> or at least very very close to spec
[16:44:09] <Xark> (re USI)
[17:15:52] <Jartza> maybe I'll try without irq first
[17:31:00] <Jartza> ouch
[17:31:01] <Jartza> yes
[17:31:10] <Jartza> hsync needs to be drawn during vsync
[17:31:12] <Jartza> that's it
[17:34:32] <Jartza> I have a stable picture
[17:35:45] <Jartza> I was already almost losing my mind thinking "this monitor CAN'T be this picky that some nanosecond makes a difference"
[17:36:00] <Jartza> well. it wasn't
[17:36:08] <Jartza> I just stopped hsync during vsync
[17:37:28] <Jartza> https://drive.google.com/file/d/0B2dTzW9TMeBxZS1TSWc4TjNVOTg/view
[18:56:07] <Jartza> yeah
[18:56:08] <Jartza> it works
[18:56:08] <Jartza> https://drive.google.com/file/d/0B2dTzW9TMeBxY05TdHgwRkw4WGc/edit
[22:04:54] <Xark> Jartza: Right on. :)