Back
[03:46:54] <EI24> It would be neat if when BREQ is true, that Z flag is automatically cleared.
[03:47:20] <EI24> the same with other branch instructions
[06:40:52] <Lambda-Aurigae> http://www.freebookcentre.net/Language/Pointers-in-C-Books.html
[06:41:17] <Lambda-Aurigae> awesome site overall and some good books and lecture slides on C pointers in this particular section.
[07:06:06] <phinxy> Whats a quick and dirty way to seal a small device from 4G interferance?
[07:28:03] <Lambda-Aurigae> aluminum foil and a grounding wire.
[07:28:39] <Lambda-Aurigae> or submerge it in a bath of grounded mercury...bit pricier though.
[10:14:17] <idiot2> Lambda-Aurigae, i'd suggest submerging it in boiling lava :)
[10:14:33] <idiot2> that is grounded well
[10:14:37] <FL4SHK> lol
[10:14:47] <idiot2> hey FL4SHK :)
[10:14:55] <FL4SHK> hey idiot2
[10:14:55] <idiot2> sup
[10:15:08] <FL4SHK> Doing GBA development right now
[10:15:14] <FL4SHK> I'm here because I sometimes do AVR stuff
[10:15:37] <idiot2> is that a drug ?
[10:15:43] <FL4SHK> nah
[10:15:54] <FL4SHK> https://github.com/fl4shk/arduinogbdump/
[10:15:59] <idiot2> ohh
[10:16:06] <idiot2> you playing with arduweenie
[10:16:25] <FL4SHK> Those are the only AVR devices I have, tmk
[10:16:36] <FL4SHK> I don't really use the IDE
[10:16:45] <FL4SHK> Mostly I've just used it to upload code
[10:20:14] <idiot2> FL4SHK, check this prototype out :)
http://dangerousprototypes.com/2012/10/24/who-says-bga-packages-are-hard-to-solder/
[10:20:38] <idiot2> bga - deadbug style
[11:50:44] <idiot2> hi
[11:56:29] <EI24> hi
[12:02:01] <LeoNerd> OK now the 32U4 is really pissing me off
[12:02:36] <LeoNerd> If I move my LED outputs off dedicated GPIOs onto a 74xx595, as is often what I do, I'll need the SPI port. But the SPI port's pins are justabuot the only PCINT lines left :(
[12:02:45] <LeoNerd> So where will I read my buttons?
[12:07:38] <LeoNerd> Seems a sad thing to do, but maybe I should bitbang my SPI :(
[12:08:31] <timemage> LeoNerd, if you have an adc input available you can try wiring the switches with different resistors as a selectable divider. not great, but it does work. alterately pair your shift out register with a shift in register, more or less turning your 595 into a proper spi device.
[12:08:48] <LeoNerd> There aren't any decent SRs that talk SPI
[12:08:56] <LeoNerd> I've spent months looking, failing to find any, ranting about it
[12:09:01] <FL4SHK> Obtain FPGA?
[12:09:03] <LeoNerd> Additionally, pinchange interrupt would be nice
[12:09:05] <timemage> LeoNerd, it's just a ordinary shift-in regiser
[12:09:07] <LeoNerd> No it isn't
[12:09:09] <idiot2> LeoNerd, i did bitbanging and works nicely for shiftregisters
[12:09:19] <timemage> LeoNerd, well, i've done it, sometime i the last half year
[12:09:19] <idiot2> any pin
[12:09:46] <timemage> LeoNerd, using something like a 595 and 165 (or 164; don' remember) wired together as a spi device.
[12:09:48] <LeoNerd> timemage: name me /any/ parallel-load SR that has tristate SDO pin, and asynchronous load that captures the parllel inputs at falling SS edge
[12:09:49] <LeoNerd> I don't know of any
[12:09:56] <LeoNerd> The 74xx165 fails on both counts
[12:10:19] <timemage> LeoNerd, if you're saying that it means i don't know what you're asking. because it didn't fail for me.
[12:10:43] <EI24> LeoNerd: are you programming the 32U4 in asm?
[12:10:47] <LeoNerd> You can read a '165 *with some help*
[12:10:49] <EI24> just curious
[12:11:12] <LeoNerd> First you need to invert the sense of the LOAD line from what you'd use as your SS... the 165's LOAD pin needs to be HIGH for serial readout, not low.
[12:11:34] <LeoNerd> Secondly, you need some way to tristate-buffer the serial output (Q7) from the 165 onto the SPI bus, as the 165 is never hiZ on output, so it will clash with other SPI devices
[12:11:46] <LeoNerd> Combined, these two facts make it awkward to use a 165 as a serial-read SR over SPI
[12:12:05] <timemage> LeoNerd, okay, so apparently i didn't see what i saw =)
[12:12:09] <twnqx> LeoNerd: yeah, that PCINT/SPI overlap is annoying me, too
[12:12:12] <idiot2> a 74HC device can be bitbanged at very high rate...
[12:12:12] <LeoNerd> EI24: Nope, C. I don't have anything sufficiently timing-critical on this particular application
[12:12:35] <EI24> Ok :)
[12:12:42] <LeoNerd> idiot2: Yeah.. It just seems a shame to bitbang an SPI protocol over some other GPIO pins simply because I can't use the real SPI hardware because of the pin clash
[12:12:50] <EI24> what do you thing of the MCU?
[12:12:52] <EI24> think*
[12:12:53] <idiot2> no it is not
[12:12:54] <LeoNerd> *ONCE AGAIN* Atmel,.. come on seriously with the crossbar switched hardware pins!
[12:13:07] <twnqx> just get an arm
[12:13:11] <twnqx> same price point anyway
[12:13:23] <idiot2> :)
[12:13:33] <idiot2> twnqx, dma the data to the shiftregister?
[12:13:39] <LeoNerd> timemage: Ohyeah, also how do I get pinchange interrupts out of a 165? ;)
[12:13:42] <twnqx> small TI tiva 4... if just programming them wasn't so much of a pain
[12:13:45] <FL4SHK> If you use an ARM, you might want to consider using Thumb mode
[12:13:54] <twnqx> as in, writing the flash
[12:13:57] <twnqx> not writing the software
[12:14:03] <LeoNerd> timemage: What I *really* want is a chip that is readable over *true* SPI, and offers me pinchange interrupts on opencollector
[12:14:13] <timemage> LeoNerd, you don't. if you want something like that i'd say maybe one of those gpio expander like nxp and microchip make.
[12:14:17] <LeoNerd> Its pins would be: D0 to D7, MOSI/MISO/SCK/SS, IRQ.
[12:14:22] <LeoNerd> Ohyhes, those. Those fine things that come in SPI forms.
[12:14:27] <LeoNerd> Ohwait, no they don't. They're only I2C
[12:14:32] <FL4SHK> Why don't you use an FPGA?
[12:14:41] <timemage> LeoNerd, yes, they do. nxp does. i've used one.
[12:14:44] <LeoNerd> Or some stupid-ass variant of I2C that uses SPI-like pins but *still* needs an initial command/addressing byte
[12:14:48] <FL4SHK> And maybe a resistor DAC if you need analog output
[12:14:55] <LeoNerd> Which contains the "slave address" which must still match the A0-A2 hardware pins
[12:15:12] <twnqx> microchip might actually make SPI...
[12:15:22] <LeoNerd> FL4SHK: Because I don't have one to hand, and won't be able to get one in the next ~5 days. And haven't had years of experience programming one
[12:15:25] <twnqx> never saw spi ones from NXP
[12:15:29] <FL4SHK> Ah okay
[12:15:30] <LeoNerd> Yes; Microchip do. It has silly SPI
[12:15:38] <idiot2> FL4SHK, fpga is expensive
[12:15:42] <twnqx> it's not
[12:15:50] <FL4SHK> There are cheap FPGAs
[12:15:56] <idiot2> costs much more than an arm
[12:15:59] <twnqx> does it
[12:16:00] <timemage> twnqx, they don't have near as many skus. but then, they're the i2c people.
[12:16:01] <FL4SHK> Not sure about FPGA boards, but FPGAs themselves can be pretty cheap
[12:16:05] <LeoNerd> Regardless: I don't have one to hand.
[12:16:05] <twnqx> cheapest i found are <5€
[12:16:15] <idiot2> twnqx, those are very limited in logic
[12:16:19] <twnqx> are they?
[12:16:22] <idiot2> yep
[12:16:26] <twnqx> the lattice ones looked pretty nice in my tests
[12:16:35] <twnqx> like, 5% usage for an spi receiver
[12:16:39] <twnqx> with 32bit
[12:16:41] <idiot2> i was looking at xilinx and altera devices
[12:16:51] <idiot2> the smallest ones being cpld with falsh builtin
[12:16:54] <FL4SHK> How do you load a bitstream onto an FPGA btw?
[12:16:55] <twnqx> yeah
[12:16:59] <FL4SHK> I only have an FPGA board where that's automatic
[12:17:01] <twnqx> "depends"
[12:17:04] <FL4SHK> Hm
[12:17:10] <FL4SHK> Okay, assuming an Altera board
[12:17:14] <FL4SHK> *altera FPGA
[12:17:16] <twnqx> personally, i'd use SPI slave mode and load from µC on boot
[12:17:40] <FL4SHK> FPGAs have SPI slave mode then?
[12:17:41] <twnqx> alternatively, drop a flash on the board and use SPI master mode
[12:17:53] <idiot2> fpgas can do any protocol you put in it :)
[12:17:54] <twnqx> not sure about altera, but xilinx and lattice do
[12:18:01] <idiot2> fpga is a programmable gate array
[12:18:04] <twnqx> idiot2: he means for configuration loading
[12:18:08] <FL4SHK> ^
[12:18:09] <idiot2> oh
[12:18:15] <idiot2> they use a tiny flash chip
[12:18:22] <twnqx> that's one of the options
[12:18:27] <idiot2> or cplds have internal flash
[12:18:34] <twnqx> parallel master, parallel slave, spi master, spi slave, internal flash, ...
[12:18:39] <twnqx> so many options
[12:18:58] <twnqx> all depends on vendor and actual chip
[12:19:05] <idiot2> twnqx, do you like spacewire ?
[12:19:14] <twnqx> never heard of that before
[12:19:16] * twnqx googles
[12:19:25] <idiot2> ieee 1394a
[12:19:55] <idiot2> they use it on spacecraft and aeroplane bus
http://bbs.dianyuan.com/bbs/u/34/1129079742.pdf 1394a std
[12:19:57] <twnqx> never used it myself
[12:20:16] <twnqx> and 1394a... is firewire
[12:20:21] <idiot2> it has good jitter tolerance
[12:20:22] <EI24> Is there a big difference between altera and xilinx? xilinx fpga s are more exapensive iv'e noticed
[12:20:34] <twnqx> i just never used altera before
[12:20:39] <EI24> like simple board for at least 25$
[12:20:43] <twnqx> since i started with xilinx in university
[12:20:54] <idiot2> EI24, you odn't buy a board if you want cheap
[12:20:55] <EI24> but for altera i bought one for 13$
[12:21:07] <idiot2> you solder the chips
[12:21:22] <EI24> idiot2: yes but configuring a fpga is really hard i've heard
[12:21:29] <idiot2> no
[12:21:32] <twnqx> no
[12:21:38] <EI24> dave jones on eevblog did a video on that
[12:21:45] <idiot2> it is just, there are no opensource tools for them
[12:21:52] <twnqx> again
[12:21:54] <twnqx> depends
[12:22:01] <twnqx> there are for xilinx jtag :P
[12:22:22] <twnqx> also, if you use spi slave, even a bus pirate can do
[12:22:37] <idiot2> well at least you can program your stuff that was "compiled" with the 8GB xilinx developer suite demo
[12:22:43] <EI24> https://www.youtube.com/watch?v=AZInaAaDlvE
[12:22:56] <EI24> here is how hard it is, accordning to him
[12:23:18] <idiot2> it is relative
[12:23:28] <twnqx> first of all
[12:23:32] <twnqx> don't use 5V
[12:23:34] <twnqx> use 3.3
[12:23:45] <idiot2> if you exercise more you will lift heavier things with less effort
[12:24:12] <twnqx> but
[12:24:16] <twnqx> he explains jtag
[12:24:23] <twnqx> which is actually the MOST DIFFICULT OF THEM ALL
[12:24:47] <twnqx> every vendor documents serial slave mode
[12:25:00] <twnqx> which is the way to go, unless you want perma flash
[12:25:15] <idiot2> twnqx,
http://en.wikipedia.org/wiki/Data_strobe_encoding :)
[12:25:18] <idiot2> ;)
[12:25:19] <twnqx> then you wither need to threestate so you can just write to the flash ship using spi
[12:25:25] <twnqx> chip*
[12:25:34] <twnqx> and still are done
[12:25:43] <twnqx> (actually, you just need to keep the fpga in reset)
[12:26:11] <EI24> it would be awesome to build your own fpga board ;p
[12:26:11] <twnqx> or, which is what xilinx does, load a core into the fpga using jtag that then allows you to program the spi chip
[12:26:20] <twnqx> been there done that
[12:26:24] <twnqx> what's the prob
[12:26:33] <twnqx> add a ft2232 for jtag programming, comes with open source
[12:27:53] <LeoNerd> AHa. I have /an/ idea. If I move my LEDs onto SPI, then with the remaining PCINT pins I'm one short for buttons. But ... I have INT6 spare. :) So I'll use that
[12:27:59] <twnqx> http://i.imgur.com/lCdy9uF.jpg
[12:28:28] <twnqx> look, an fpga board with USB2JTAG + USB 2.0 daughterboard, and 5V tolerant IO to fit into a 40pin DIL socket!
[12:28:53] <EI24> how much is it?
[12:29:10] <twnqx> never calculated the cost
[12:29:15] <twnqx> built it myself, so... expensive
[12:29:20] <EI24> ohh cool
[12:29:27] <EI24> did you design the pcb?
[12:29:39] <twnqx> yeah, both of them
[12:29:55] <EI24> nice... :o
[12:31:40] <idiot2> anybody made a usb flashdrive/ssd yet ?
[12:31:59] <idiot2> or sata ?
[12:36:45] <EI24> gah, EIJMP isn't supported on m328p i need to be able to jump to a adress from loaded two registers somehow
[12:39:36] <timemage> EI24, can you stack them and then jut ret?
[12:39:43] <timemage> err, just.. ret.
[12:39:49] <idiot2> :)
[12:40:12] <idiot2> push push ret16?
[12:42:07] <EI24> timemage: i found IJMP instead it works even better :)
[12:42:49] <timemage> EI24, alright. maybe i'll just sleep for the rest of the day.
[12:44:36] <EI24> i trying to program a function that starts the counter, and on overflow interrupt jumps to different locations based a stored number in sram
[12:45:48] <idiot2> timemage, summon some cool stuff
[12:46:29] <EI24> timemage, wasn't that a creature from yugioh? haha
[12:46:48] <EI24> ops no ping intended
[13:03:20] <EI24> when writing in hex there are two notations used 0x nad $. As i've understood there are no diffrence. But are they used in different context to imply something? maybe like, to only use $ when meaning flash or SRAM addresses?
[13:04:13] <LeoNerd> Mmm?
[13:07:14] <EI24> like: LDI r16 , 0x8F and STS $8F , r16
[13:08:15] <EI24> $8F and 0x8F mean the same, but maybe one uses 0x and $ in different contexts
[13:08:28] <EI24> like above
[13:46:29] <LeoNerd> Well, there we are. An hour or so of rearrangeing board layout and code later, I've managed to arrange all my LEDs off the PCINT-capable pins, so I can put my buttons there, and instead hang my LEDs off a 595 attached to the SPI port. I'm not sure I've achieved a *lot* yet, but at least I can easily add more LEDs via SR if I need them
[13:46:33] <LeoNerd> Which is a start
[14:08:12] <timemage> EI24, C uses 0x, $ was more common in assembly historically. some basics dialects also used $ notation. some assemblers let you do both for convenience.
[14:09:05] <timemage> nice.
[14:16:44] <idiot2> i have an idea doing software ecc, but still the cpu and cache memory is vulnerable too, though they are much smaller in area than the ddr memory cards, you need to store and read ecc way your data, so basically overhead for every single read and write, and you can "resilver" the memory at any rate to check if everything is fine, and fix erroneous bits it would be a ghetto ecc memory for your pc, the last thing that could be done it to check
[14:16:44] <idiot2> the integrity of the ecc code itself if there are 2 dentical functions, one can check the other - hopefully for example, but the thing requires the running sotfware to not get corrupted, could some kind of interrupt/dma help in this?
[14:20:51] <idiot2> btw lold :) #irc.freenode PIC vs Atmel AVR short comparison
http://pastebin.com/m4Fkg5R2
[14:27:34] <EI24> idiot2: haha, i've heard of this PIC vs AVR war
[14:29:40] <angry_specing> funny thing it, a stm32f030 would replace all those PICs and some AVRs and would cost about 50 cents.
[14:29:48] <idiot2> :)
[14:30:13] <idiot2> i just heard things about pic's internal build quality too and i can say it is not for industrial use
[14:30:17] <EI24> it's so funny how people can be religious about peculiar things x)
[14:30:21] <idiot2> also take a look at the asm lol.
[14:30:55] <idiot2> a brainfuck code works too ofc i'm not argueing about that
[14:31:26] <angry_specing> I find it weird that there are no >100MHz AVRs/PICs
[14:33:17] <idiot2> oh
[14:33:24] <Xark> angry_specing: There is PIC32 (233MHz).
[14:33:28] <idiot2> atmel arm can do 64MHz
[14:33:52] <idiot2> and i saw a similar nxp arm that does 100MHz+
[14:34:09] <idiot2> (i mean the cheap atmel arm)
[14:34:16] <idiot2> there are 400MHz ones too
[14:41:47] <angry_specing> Xark: that is not a PIC
[14:41:54] <angry_specing> idiot2: that is not an AVR
[14:42:01] <Lambda-Aurigae> cheap pic32 in a 28pin dip package with hardware usb can do 50MHz.
[14:42:13] <angry_specing> Lambda-Aurigae: that is not a PIC
[14:42:14] <Xark> angry_specing: PIC32 from Microchip. Depends on your definition.
[14:42:20] <Lambda-Aurigae> I know.
[14:42:22] <angry_specing> THAT IS NOT A PIC!!!!!!!!!!!!!
[14:42:29] <angry_specing> GODDAMN IT!!!!!!
[14:42:29] <Lambda-Aurigae> it's a mips core.
[14:42:34] <Xark> angry_specing: Only PICs I used, so I disagree.
[14:42:38] <Lambda-Aurigae> that's why I said pic32...
[14:42:51] <angry_specing> I know there are mips and arm over GHz
[14:43:01] * Xark avoids the crappy 8 and 16 bit PICs
[14:43:06] <angry_specing> but I know of no 8-bit micros at > 30 MHz
[14:43:14] <Lambda-Aurigae> I use some of the 8bit pics for usb interface devices.
[14:43:20] <Xark> angry_specing: STC 8051 runs at 40MHz
[14:43:20] <angry_specing> which is what AVRs and PICs are
[14:43:25] <angry_specing> Xark: ok
[14:43:30] <angry_specing> Xark: now >50 MHz?
[14:43:51] <Lambda-Aurigae> used to be a pic clone that was 50MHz.
[14:44:15] <Xark> They exist. Here is a x86 emulated with fast 8051 (IIRC, like 100MHz). ->
http://www.fleasystems.com/flea86.html
[14:44:46] <angry_specing> Lets get this straight
[14:44:59] <Lambda-Aurigae> I use 32MHz 8052 chips on occasion too...with single instruction cores.
[14:45:04] <angry_specing> tell me of a hardware implementation of a >100 MHz 8-bit core
[14:45:09] <Xark> Appotech's AX-2005
[14:45:33] <Xark> E.g., 144MIPS ->
http://www.mcupower.com.hk/EN/Products.php?b=Appotech
[14:48:36] <EI24> 144 mips.. damn
[14:49:31] <Lambda-Aurigae> paralax sx series run up to 75MHz with single instruction cores...
[14:49:36] <Xark> (A cousin of the chip used in the PC emulator linked above)
[14:50:38] <Xark> Lambda-Aurigae: Yeah, the former UBICOM stuff.
[14:50:47] <Lambda-Aurigae> yup...scenix
[14:50:56] <Lambda-Aurigae> they only have one chip left they are making.
[14:50:57] <Xark> Dead now though, right?
[14:51:00] <Lambda-Aurigae> with 4K flash.
[14:51:05] <Lambda-Aurigae> https://www.parallax.com/product/sx48bd-g
[14:51:15] <Lambda-Aurigae> oh..
[14:51:18] <Lambda-Aurigae> nevermind..end of life.
[14:51:42] <Lambda-Aurigae> still 93092 in stock though.
[14:52:02] <EI24> if a a 8-bit chip is the same size as a 16 or 32-bit. is there any benefit of using 8-bit? (other the cost maybe)
[14:52:21] <Xark> EI24: Not really
[14:53:40] <Lambda-Aurigae> the main reason I use 8bit microcontrollers is ease of use because very few 32bit are available in dip package.
[14:54:13] <EI24> ok, well then it seems weird to make the bigger ones
[14:54:23] <Xark> AFAIK, PIC32 and NXP1114 (and LPC810...)
[14:55:05] <EI24> i like the paralax, 8 cores ^^ i heard there is commming a paralax propeller 2 soon
[14:55:14] * Xark recently bought just about every 16-bit and 32-bit chip in DIP from Mouser. :)
[14:55:25] <EI24> open source hardware also!
[14:55:38] <EI24> Xark: wow, did it cost much?
[14:56:01] <Xark> EI24: There are are only like four chips, so no.
[14:56:20] <Lambda-Aurigae> Xark, there are at least 2 from microchip in the 32bit range in dip package.
[14:56:33] <Xark> PIC32, NXP1114, LPC810 and (as you reminded me) Parallax Propeller
[14:56:45] <Xark> Lambda-Aurigae: Yeah, those are the PIC32, right?
[14:56:49] <Lambda-Aurigae> yup
[14:57:21] <Lambda-Aurigae> pic32mx250f128b and pic32mx270f256b
[14:57:22] <Xark> I got the biggest available (PIC32MX250F128B IIRC)
[14:57:28] <Lambda-Aurigae> nope
[14:57:34] <Lambda-Aurigae> 270 is bigger
[14:57:38] <Xark> (That Mouser had available)
[14:57:41] <Lambda-Aurigae> cougle the flash and ram.
[14:57:43] <Lambda-Aurigae> double
[14:58:02] <Lambda-Aurigae> 256K flash and 64K sram.
[14:58:12] <Xark> I wasn't stocked, IIRC
[14:58:16] <Xark> It*
[14:58:23] <Lambda-Aurigae> got some as free samples a month or so ago.
[14:59:19] <EI24> PIC24FJ256DA206 seems very interesting, 3 gpu's though i wonder what the gpus really do
[14:59:31] <Lambda-Aurigae> graphic processing.
[14:59:42] <EI24> yes ofc but, like more specific
[15:00:10] <Lambda-Aurigae> for video output.
[15:00:17] <Lambda-Aurigae> it's a display interface chip.
[15:00:21] * Xark has a few devboards with the 512KB SRAM PIC32 parts (bit not DIP).
[15:01:13] <Lambda-Aurigae> Xark, yeah...there are some with lots of ram onboard and some of the pic32 chips even have external ram interfaces.
[15:01:46] <EI24> yeah, they it has the ram for a framebuffer, but if the display driver already has built in ram for that, why have another framebuffer
[15:02:54] <Xark> EI24: So CPU has easy access to pixels?
[15:03:19] <EI24> oh, right haha
[15:03:26] <EI24> hahaha
[15:04:53] <Lambda-Aurigae> frame----buffer.
[15:05:13] <Lambda-Aurigae> write to the framebuffer then tell the gpu to update the active frame from the framebuffer.
[15:05:53] <EI24> ok, but why 3 gpus?
[15:06:01] <Lambda-Aurigae> why not?
[15:06:02] * Xark checks - his PIC32 devboard has PIC32MX795F512H (80MHz with 512KB flash and 128KB RAM) -> https://atomsoft.wordpress.com/atom32/ (showing it running Retro-BSD). :)
[15:06:13] <Lambda-Aurigae> for doing multiple things on your graphic display.
[15:06:22] <Lambda-Aurigae> processing 3D graphics.
[15:07:53] <EI24> You think it would be able to output 3D graphics?
[15:07:57] <Lambda-Aurigae> sure.
[15:08:05] <EI24> that powerful
[15:08:10] <Lambda-Aurigae> heck, I can output 3D graphics with an AVR on a TV.
[15:08:10] <EI24> thats*
[15:08:16] <Lambda-Aurigae> not particularly fast,,,but,,
[15:08:16] <EI24> what!
[15:08:55] <EI24> Xark: you should make like a blog for all you libs and other nice stuff you've done
[15:09:03] <Lambda-Aurigae> https://www.youtube.com/watch?v=LUDM_oSndOY
[15:09:25] <EI24> the things i've seen have been pretty nice
[15:09:36] <Lambda-Aurigae> https://www.youtube.com/watch?v=QzRpOgtcoag
[15:09:55] <Lambda-Aurigae> https://www.youtube.com/watch?v=t-fPCPEx7bY
[15:10:59] <EI24> that pretty neat
[15:11:07] <Lambda-Aurigae> that pic can probably do much better.
[15:11:51] * Xark works on getting his AVR 6502 core running from flash & SRAM today (Xark is not a fan of non-unified address space on AVRs...)
[15:12:02] <idiot2> http://www.nxp.com/products/microcontrollers/product_series/lpc1700/LPC1786FBD208.html :) 120MHz arm
[15:12:16] <idiot2> cortex M3
[15:13:00] <idiot2> something like this
http://www.atmel.com/devices/sam3s1c.aspx
[15:13:03] <idiot2> some differences
[15:14:07] <idiot2> half speed, but works fownto 1.8V :/ though the atmel arm has the samba craploader
[15:14:27] <idiot2> pros cons
[15:14:45] <EI24> yeah those look nice
[15:15:25] <idiot2> both is cheap and fairly powerful
[15:16:14] <EI24> the first one has much more flash and sram, though maybe you dont need as much
[15:17:13] <idiot2> in code, not really, but you may prefer storing midi files, or text strings or logs
[15:17:46] <idiot2> or bitmap fonts
[15:21:32] <EI24> Xark: oh maybe that was your blog/shop
[15:21:49] <Xark> Nope, not mine.
