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[00:08:09] <Casper> hey anonnumberanon... maybe you need a turbo encabulator? ===>
https://www.youtube.com/watch?v=Ac7G7xOG2Ag
[00:17:42] <anonnumberanon> Casper, all I need is H20 and other gases.
[00:19:36] <Casper> nahhh you need a free turbo encabulator, so you can resell it for 10% of it's pricetag! :D
[02:46:41] <jaggzt> Casper! o/
[05:58:43] <NicoHood> any idea why i get this LOW peek at the beginning? it shouldnt be there. i set the pin high before the mode change and after. and at the beginning of the asm.
[05:58:44] <NicoHood> https://gist.github.com/NicoHood/65fd66c3905126cdd2d8
[05:58:44] <NicoHood> http://i.minus.com/ibtEEkfX2gmEaW.PNG
[08:16:33] <vsync> losing my marbles on this nrf8001, upon reset the chip enters setup-state. I can verify this, and in this state it should accept the configuration data i'm sending it. However it just responds with device state invalid.
[08:17:42] <LeoNerd> Are you on the Nordic Semi. forum, by the way? Could try asking there as well
[08:17:49] <LeoNerd> (if it's more of an nRF than an AVR question)
[08:35:06] <LeoNerd> So. Hrm.. By various accounts, there are four different SPI modes (some people call it mode 0/1/2/3, some use CPOL/CPHA, some use other naming). I'm struggling to understand why four different arrangements are required. I can only see two different things: whether the rising vs. falling edge of the clock matters.
[08:35:30] <LeoNerd> In two modes, data is clocked on the rising edge; in two others, on the falling. So how come there are four choices - what's the other distinction that matters?
[08:37:50] <Lambda_Auriga_> you have clock polarity and clock phase.
[08:38:12] <Lambda_Auriga_> giving you the 4 modes.
[08:38:37] <LeoNerd> Yes. I'm aware that there are four settings
[08:38:39] <LeoNerd> I don't know *Why*
[08:38:41] <Lambda_Auriga_> http://www.byteparadigm.com/applications/introduction-to-i2c-and-spi-protocols/
[08:38:45] <LeoNerd> What *practical* difference will matter?
[08:38:55] <Lambda_Auriga_> the "why" is a mystery.
[08:39:01] <LeoNerd> I don't care about history
[08:39:09] <LeoNerd> I want to know what one single thing could possible ever actually break, if it was wrong
[08:39:25] <LeoNerd> I can understand why if the data is shifted on the wrong edge of the clock signal, that would be bad
[08:39:39] <LeoNerd> I can't understand a single other thing that would make a difference between "this works" and "this doesn't work"
[08:40:35] <Lambda_Auriga_> you have clock idle high and clock idle low as well as clock edge.
[08:41:43] <LeoNerd> Yes. I'm aware
[08:41:51] <Lambda_Auriga_> if your clock idle level is wrong then it won't work.
[08:41:53] <LeoNerd> Name me one circuit anyone ever built in the world, that cares if the clock idles high or low
[08:42:00] <Lambda_Auriga_> SPI
[08:42:02] <LeoNerd> GAHH
[08:42:05] <LeoNerd> I want to know details
[08:42:11] <Lambda_Auriga_> on what?
[08:42:31] <LeoNerd> One case: clock idles HIGH, I set up first data bit on MOSI, I pull clock low, then HIGH => data gets clocked in
[08:42:36] <Lambda_Auriga_> I posted a link that shows the details on the phase and polarity.
[08:42:50] <LeoNerd> Other case: clock idles LOW, I set up data bit on MOSI, I push clock high => data gets clocked in, then I pull clock LOW again
[08:42:53] <LeoNerd> WORKS THE SAME in both cases
[08:43:01] <LeoNerd> I do not undersatnd why the circuit cares if the idle is high or low
[08:43:52] <LeoNerd> Let me make it clearer: I don't understand why either chip at either end of the SPI link cares any more whether the clock *idles* low or high, than it cares what colour plastic the wire is insulated in
[08:49:59] <Ebola-C> hard question
[08:50:01] <Lambda_Auriga_> I can see that various chips would have different requirements...possibly for different manufacturers not wanting to be compatible with each other...no clue as to why they did it..
[08:50:02] <Lambda_Auriga_> but
[08:50:38] <Lambda_Auriga_> it does seem very possible that some chips could only work with certain polarity clock..
[08:52:21] <Lambda_Auriga_> a couple of sites I've looked at talk about how some chips ignore polarity and others don't.
[08:52:23] <LeoNerd> I dpn't understand how
[08:52:31] <LeoNerd> Concrete example: 74HC595
[08:52:44] <LeoNerd> It shifts the DI->Qchain->DO bits on a _falling_ edge of the clock line
[08:52:51] <Lambda_Auriga_> by looking at the clock line when the /SS pin goes low...
[08:53:00] <LeoNerd> Nothing else matters. This chips does not care if the clock line sits around idle at high or low
[08:53:13] <Lambda_Auriga_> that is one of the chips that doesn't care...and I would think the simple shift registers don't care in general.
[08:53:19] <LeoNerd> All it cares about is that I hold my bit on MOSI into its DI, at the time I _lower_ the clock line
[08:53:22] <LeoNerd> OK
[08:53:40] <Lambda_Auriga_> but active SPI interfaces might look at all the lines at the same time and wait for a certain set of circumstances..
[08:53:43] <LeoNerd> So now we're getting somewhere. So if the 595 doesn't care, can you illustrate an example of a different (even hypothetical) chpi, that will?
[08:53:55] <Lambda_Auriga_> I just did.
[08:54:02] <Lambda_Auriga_> a chip that watches the SS and CLK lines
[08:54:36] <Lambda_Auriga_> if the CLK line is low,,idle,,when the SS goes low then it goes active...if the CLK is high,,not idle,,when the SS goes low it ignores the activation.
[08:54:44] <LeoNerd> Ah; something that would sample the level of SCK at the falling edge of SS?
[08:54:48] <Lambda_Auriga_> that would be polarity 0.
[08:54:54] <Lambda_Auriga_> yes.
[08:54:57] <LeoNerd> Hmm...
[08:55:05] <Lambda_Auriga_> http://support.saleae.com/hc/en-us/articles/200895130-Learn-SPI-Serial-Peripheral-Interface
[08:55:09] <Ebola-C> good question
[08:55:11] <LeoNerd> Thus giving it a start condition that looks similar to I2C-style ones
[08:55:14] <Lambda_Auriga_> has timing charts for the 4 modes.
[08:55:16] <LeoNerd> Yesyes
[08:55:18] <Lambda_Auriga_> yes.
[08:55:19] <LeoNerd> I KNOW WHAT THEY LOOK LIKE
[08:55:22] <Lambda_Auriga_> ok.
[08:55:32] <LeoNerd> I keep saying: I know *what* they do, I don't know *how* that distinction would ever matter
[08:55:50] <Tom_itx> dude! stop shouting... i just woke up
[08:55:51] <Lambda_Auriga_> because the maker of the chip made it matter.
[08:56:06] <LeoNerd> Keep in mind my quesiton: I don't understand how the difference of clock idle state matters more than the colour of insulation plastic
[08:56:31] <Ebola-C> there is discusion about how SPI works.. It seems like LeoNerd try to make his own SPI IC
[08:56:47] <Lambda_Auriga_> you never watched movies where they disable bombs do you? Color of wire ALWAYS matters! :}
[08:56:51] <LeoNerd> The chip does not and cannot know the plastic colour. Surely by the same argument, the chip does not and cannot know the difference between "idle" and "damn he's taken 3 minutes to clock this one bit out"
[08:57:31] <Lambda_Auriga_> but the chip can know...a simple shift register won't but a fully active SPI chip might.
[08:57:41] <Ebola-C> you find the way how to slow down electrons? WOW!
[08:57:57] <LeoNerd> How does it know?
[08:58:05] <LeoNerd> Are you suggesting the SS line is the key here?
[08:58:11] <LeoNerd> If we ignore the SS line, then does it matter?
[08:58:19] <Lambda_Auriga_> I don't know.
[08:58:30] <Lambda_Auriga_> I have run into some chips that won't work unless the /SS toggles.
[08:58:52] <Tom_itx> SS wakes up the target chip
[08:58:53] <LeoNerd> Ohsure.. many chips I've seen do that.. you have to perform an SS transition to start a single "transactoin"
[08:59:13] <Tom_itx> CPOL CPHA is the native language we will be speaking
[08:59:15] <Lambda_Auriga_> and, the chip could be watching the CLK line at the same time.
[08:59:32] <Tom_itx> clock is how fast we plan to have the discussion
[08:59:37] <Lambda_Auriga_> operative, "could"
[08:59:38] <LeoNerd> Hmm...
[09:01:48] <Lambda_Auriga_> the wikipedia has a real good timing diagram that shows the real differences in timing for the 4 modes.
[09:01:56] <Lambda_Auriga_> http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus#mediaviewer/File:SPI_timing_diagram2.svg
[09:02:00] <LeoNerd> Yesyes.. I can draw those diagrams as well
[09:02:16] <LeoNerd> I can also draw a diagram in which the MOSI line wiggles around while the clock is "idle". That wouldn't make a difference
[09:05:01] <Lambda_Auriga_> again, for those who don't hate wikipedia, there is a good writeup on the wikipedia page about how the polarity and phase make the 4 modes different.
[09:05:54] <LeoNerd> I know WHY they are different
[09:06:02] <LeoNerd> (gah netsplit)
[09:06:55] <Lambda_Auriga_> oops.
[09:06:57] <Lambda_Auriga_> again, for those who don't hate wikipedia, there is a good writeup on the wikipedia page about how the polarity and phase make the 4 modes different.
[09:07:15] <LeoNerd> Lambda_Auriga_: Again: there are many chips that care that I get the mode right. Suppoes I told you I had a chip here that cares that I only use a red wire on the SCK line, and not a blue wire.
[09:07:29] <LeoNerd> You would (hopefully) tell me I'm obviously an idiot because the chip can't know, can't care about that
[09:07:45] <LeoNerd> What I am saying is that I can't see how the chip can know or care about the idle state
[09:07:48] <LeoNerd> What is "idle"?
[09:07:49] <Lambda_Auriga_> but it can know and care about voltage levels on communications wires.
[09:07:57] <LeoNerd> The clock goes up and down.
[09:08:00] <Lambda_Auriga_> idle means it's not doing anything...means idle.
[09:08:09] <LeoNerd> When it goes (either up or down depending on the mode), a bit is clocked forwards.
[09:08:14] <LeoNerd> Every eight clocks, that's a byte of data.
[09:08:20] <LeoNerd> Explain where in this the "idle" happens
[09:08:37] <LeoNerd> Explain where half the chips in the world work and half do not, depending on whether the idle is high or low
[09:08:41] <Lambda_Auriga_> idle state is between bytes or between blocks.
[09:08:50] <LeoNerd> But why does that matter?
[09:09:00] <Lambda_Auriga_> because someone made the chip so it does?
[09:09:09] <LeoNerd> OK we're going around in circles here
[09:10:36] <Tom_itx> LeoNerd, those questions are answered with CPOL CPHA
[09:10:44] <LeoNerd> No they're not. they're really not
[09:11:05] <Tom_itx> and the data length
[09:11:06] <Lambda_Auriga_> LeoNerd, I think you are thinking that all SPI is just a simple shift register....and not all SPI devices are simple shift registers.
[09:11:07] <LeoNerd> I can easily draw you four separate timing diagrams showing the four separate cases of CPOL/CPHA or mode numbering or whatever
[09:11:13] <Tom_itx> which is usually in a data sheet
[09:11:40] <LeoNerd> I cannot think of ANY POSSIBLE WAY I could ever build a circuit in silicon or on a microcontroller or anything, that would possibly care about anything *other* than the rising-vs-falling direction of the clock line
[09:11:49] <Lambda_Auriga_> I can.
[09:12:01] <LeoNerd> Then please explain it to me. Explain how you'd make a circuit that can tell
[09:12:06] <Lambda_Auriga_> already have.
[09:12:14] <LeoNerd> By sampling SCK at SS falling time?
[09:12:17] <Lambda_Auriga_> when one line changes state, look at the state of another line.
[09:12:30] <Lambda_Auriga_> do it all the time with rotary encoders.
[09:12:53] <Lambda_Auriga_> 4 pins..2 are clocking points and the other two are stable points that are read during changing points on the clocking lines.
[09:13:00] <LeoNerd> Yesyes
[09:13:19] <LeoNerd> So specifically to SPI: can you make a distinction by looking *ONLY* at SCK/MOSI/MISO, or do you need to consider SS as well?
[09:13:30] <Lambda_Auriga_> that depends on the chip.
[09:13:42] <LeoNerd> Forget chips
[09:13:53] <Lambda_Auriga_> some chips will not work unless the clock is in a certain state when the /SS is brought low.
[09:14:10] <Lambda_Auriga_> but that's what we are talking about..why some will work and others will not under certain conditions.
[09:14:16] <LeoNerd> OK.. simpler question: I will give you three wires, labeled SCK, MOSI and MISO. I want you to make *some kind of circuit* that displays one of FOUR LEDs, depending ont he four different SPI modes I talk down those wires
[09:14:18] <LeoNerd> Can you do it?
[09:14:29] <LeoNerd> Can you distinguish ALL FOUR cases, by only looking at my SCK/MOSI/MISO wires?
[09:14:30] <Lambda_Auriga_> if you are looking at pure SPI communications...according to the spec you must allow for CHPA and CPOL.
[09:14:46] <LeoNerd> I will state now: I cannot think of how I would make such a circuit
[09:14:47] <Lambda_Auriga_> actually, yes, I think you can.
[09:15:04] <Lambda_Auriga_> read the clock polarity and phase section of the wikipedia entry.
[09:15:12] <LeoNerd> I have done. Many times
[09:15:20] <Lambda_Auriga_> it explains it rather well to me.
[09:15:27] <LeoNerd> I don't make a habit of professing my ignorance on IRC until I'm quite sure I've tried reading about it for myself
[09:15:33] <Lambda_Auriga_> I would love to stay and work on this longer but I must go make sawdust.
[09:15:47] <Lambda_Auriga_> putting up a wall in the house today.
[09:15:49] <Tom_itx> rising or falling edge active and high or low is good data
[09:15:52] <LeoNerd> Tom_itx: woudl you be able to illustrate any better?
[09:16:04] <Tom_itx> i don't care to get sucked into this discussion
[09:16:10] <Tom_itx> :)
[09:16:18] <LeoNerd> I can easily tell the differnce between two modes, buy just looking at which _state_ of the clock line (high or low) the MOSI line changes on
[09:16:34] <LeoNerd> If MOSI changes on SCK HIGH, then we care about falling edge; if it changes on SCK LOW, then we care about rising
[09:16:35] <Tom_itx> i'm not quite awake yet...
[09:17:00] <LeoNerd> Can anyone else?
[09:17:11] <LeoNerd> A single person here in the channel - can anyone suggest how they'd make the circuit above?
[09:17:31] <Tom_itx> fpga
[09:17:39] <LeoNerd> Nono
[09:17:49] <LeoNerd> I don't care how you do it physically, I want you to explain the detecting principle it would use
[09:17:51] <Tom_itx> that was a cop out...
[09:17:54] <LeoNerd> E.g. note the way I explained above
[09:18:35] <LeoNerd> Oh hang on...
[09:18:50] <Tom_itx> <LeoNerd> So. Hrm.. By various accounts, there are four different SPI modes (some people call it mode 0/1/2/3, some use CPOL/CPHA, some use other naming). I'm struggling to understand why four different arrangements are required. I can only see two different things: whether the rising vs. falling edge of the clock matters.
[09:18:50] <LeoNerd> Is this all to do with the _bidirectional_ transfer of MOSI vs. MISO?
[09:19:02] <Tom_itx> for the same reason there were so many serial modems
[09:19:12] <Tom_itx> nobody could agree on one standard
[09:19:13] <LeoNerd> Nono.. serial modems I can understand..
[09:19:15] <LeoNerd> YES GAH
[09:19:27] <LeoNerd> If those use different standards, different things happen and A doesn't talk to B And it all breaks
[09:19:29] <LeoNerd> I'm happy with that
[09:19:43] <LeoNerd> Again FOR THE N'th TIME: I cannot see how the circuit _CAN POSSIBLY KNOW_ which setup I'm using
[09:20:05] <LeoNerd> Again I am stating I DO NOT UNDERSTAND SPI, so someone please explain it to me
[09:20:09] <Tom_itx> the master initiates the transfer
[09:20:13] <LeoNerd> Evidentally this *does* make a difference as I have seen for myself
[09:20:17] <LeoNerd> I cannot understand why it did so
[09:20:32] <Tom_itx> if it sends a wakeup packet and it doesn't wake up try another language
[09:20:39] <Tom_itx> until it finds one they can both speak
[09:20:54] <LeoNerd> Again: By observation: the 74HC595 doesn't care about the idle state of the clock
[09:21:01] <LeoNerd> Some other chips do.
[09:21:13] <LeoNerd> I want to understand what it is those chips do, where it makes a difference. And I wonder if it's the MOSI vs. MISO
[09:21:31] <Tom_itx> why?
[09:21:43] <LeoNerd> well.. me driving a 595 was just unidirectional
[09:22:16] <LeoNerd> But a proper bidirectional transfer has two things to consider: when slave reads master's MOSI, and when master reads slave's MISO
[09:22:27] <LeoNerd> Do they both happen on the *same* clock edge, or different. WP suggests opposite ones
[09:22:34] <LeoNerd> "For CPHA=0, data are captured on the clock's rising edge (low→high transition) and data is propagated on a falling edge (high→low clock transition)"
[09:22:46] <Tom_itx> they both happen at once with spi
[09:22:52] <LeoNerd> At which point it massively *does* matter what order those happen in, but only for bidirectional stuff
[09:22:53] <LeoNerd> Hrm
[09:22:58] <Tom_itx> the bits lag by one packet
[09:23:02] <Tom_itx> on the slave
[09:23:21] <LeoNerd> Well then that doesn't explain it any more :(
[09:23:26] <LeoNerd> I thought that would be enough to tell
[09:25:19] <LeoNerd> OK lets try a thought-experiment:
[09:26:11] <LeoNerd> Suppose my SPI master is outputting in clock idle low, using rising-edge for transfers: This means I hold the clock low for a while, then I set up the first MOSI bit, wait for it to be stable, then I pulse the clock ->high->low. I set up the second bit, do the same... 6 more bits... I then end up with the clock low again.
[09:26:46] <LeoNerd> So that's the master sending data. Now, if the slave device wants to read this, it will have to sample the MOSI line on the rising edge, and ignore it any other time. It will successfully read those 8 bits inbound. Do we agree?
[09:28:30] <LeoNerd> Now lets suppose instead, using *the very same slave* I decide to set a different mode in the master: In this mode I'll still use rising-edge, but this time I'll keep the clock idle-high.
[09:29:21] <LeoNerd> So I start with a high clock in idle state. I then want to start a bit, so I pull the clock down, set up my first bit on MOSI, and raise the clock. I then lower the clock, set up my second bit on MOSI, raise it again. I do this 6 more times again, and after 8 bits, I finally keep the clock high in my idle state.
[09:29:37] <LeoNerd> Using the same slave as before, the slave has *again* managed to perfectly correctly read those 8 bits off the MOSI wire.
[09:36:05] <LeoNerd> Now.. obviously if the slave was using the wrong edge for the clock, it could well get confused if I output my next MOSI bit at the same time as I lower the clock (e.g. because of a single write to the PORTx register), then there's a chance it could see my pin during transition, and it's not clear whether it would see the previous or next bit.
[09:36:11] <LeoNerd> So it's clear why the slave has to use the right edge.
[09:37:15] <Lambda_Auriga_> looks like the big difference is the cpha....with chpa=0 you have to have stable data half a cycle before initiating your first clock..with CPHA=1 it moves the transition half a clock out automatically, requiring no clock start delay...then you have the CPOL being low/high/low or high/low/high for data capture.
[09:37:32] <Lambda_Auriga_> at least, that's how I'm reading it.
[09:37:39] <Lambda_Auriga_> anyhow, back to sawdust.
[10:13:11] <Lambda_Auriga_> just found a dip package chip with 256K flash and 65K sram that runs a 32bit core at 50MHz..
[10:14:05] <Lambda_Auriga_> and has hardware USB.
[10:14:28] <LeoNerd> Mm.. some kind of ARM?
[10:18:02] <Lambda_Auriga_> nope
[10:18:04] <Lambda_Auriga_> pic32
[10:18:18] <LeoNerd> Ahyes; lots of PICs do USB
[10:18:22] <Lambda_Auriga_> yes
[10:18:26] <Lambda_Auriga_> and lots do it in dip package
[10:19:37] <Lambda_Auriga_> I think I can turn one into an 800x600 monochrome vga display adapter...
[10:35:00] <vsync> pic>avr, generally
[10:40:28] <Lambda_Auriga_> vsync, I wouldn't go that far..
[10:40:44] <Lambda_Auriga_> I prefer AVR programming over PIC...but I prefer pic hardware diversity.
[10:40:49] <LeoNerd> I think AVRs have nicer toolchain..
[10:41:28] <LeoNerd> (That said I'm still waiting for an ATmega with more of a crossbar matrix on the IO pins like all the decent PICs have now)
[10:41:58] <Lambda_Auriga_> pic32 isn't even a real pic....it's a mips processor with pic peripherals.
[10:42:18] <LeoNerd> Mmmm
[10:42:31] <Lambda_Auriga_> but their documentation still sucks horribly.
[10:43:25] <Lambda_Auriga_> I've been using the sdcc toolchain for them lately.
[11:50:21] <jaggzt> what's a good tutorial to introduce me to AVR C code? how these port variables are used and such
[11:54:40] <Lambda_Auriga_> jaggzt, I found the avr datasheet to be very informative...but that requires one to read.
[11:55:14] <jaggzt> yeah I'm downloading that now.. just read parts of the bootloader doc..
[11:55:17] <kraiskil> jaggz,
http://www.nongnu.org/avr-libc/user-manual/ , especially the examples to get you started
[11:55:21] <Tom_itx> http://tom-itx.no-ip.biz:81/~webpage/how_to/atmega168/mega168_howto_main_index.php
[11:55:22] <Lambda_Auriga_> http://tuxgraphics.org/electronics/200904/avr-c-programming.shtml
[11:55:25] <Tom_itx> http://tom-itx.no-ip.biz:81/~webpage/avr/c_bits/bits_index.php
[11:55:54] <Lambda_Auriga_> https://iamsuhasm.wordpress.com/tutsproj/avr-gcc-tutorial/
[11:56:10] <Lambda_Auriga_> google is your friend.
[11:56:42] <jaggzt> yeah.. been googling.. finding good tutorials that I get caught up in reading, but they're not exactly what I'm looking for
[11:56:44] <jaggzt> checking these out now
[11:57:26] <Lambda_Auriga_> that last one I posted goes into a lot of i/o stuff.
[11:59:30] <jaggzt> ahhh.. I think the last one might be the first to read for me
[12:00:22] <jaggzt> since I have questions like, "what are the magic variables available.. what is the naming convention.. how do I relate the variable names to the names of the pins in the data sheet (if it's not spelled out in the datasheet), ..."
[12:01:11] <LeoNerd> They're all the ones named in the data sheet for the part you're using... which ones those are depend on the part
[12:01:12] <Lambda_Auriga_> also the avr-libc user manual page is very very good.
[12:02:44] <Lambda_Auriga_> and all those magic variables are actually registers in the AVR itself.
[12:03:07] <Lambda_Auriga_> for which, the datasheet is your best resource.
[12:04:32] <Lambda_Auriga_> the avr-libc and avr/io.h and associated header files have definitions for all of those registers so you don't have to remember register numbers and bits.
[12:04:33] <jaggzt> thanks :)
[12:05:01] <jaggzt> Once I do my first program perhaps I'll examine some of the ASM too..
[12:05:16] <Lambda_Auriga_> there are so many resources out there on the web these days...far more than when I started with AVR back in around 2000.
[12:05:33] <jaggzt> I haven't yet done my first, which is to just print a string in a loop and read it over usb
[12:05:53] <Lambda_Auriga_> I'm guessing you have a usb-serial adapter?
[12:06:27] <jaggzt> yes x 2. I have Tom's, but these leonardo micros were the proper size, and with my desired chip, to put in a mouse for someone
[12:06:54] <jaggzt> well, just buttons.. they're having problems using a mouse now.. so one hand is mouse-movement, the other is buttons..
[12:07:35] <Lambda_Auriga_> I would just use two mice..cover the optical movement bit on one and break the buttons on the other.
[12:07:48] <jaggzt> Tom, by the way, Casper referred me to you to get the programmer :)
[12:08:09] <jaggzt> oh.. usb-serial.. I'm confusing that with programmer.
[12:08:27] <Lambda_Auriga_> the way to get the AVR communicating with the computer via USB.
[12:08:45] <Lambda_Auriga_> unless your AVR has hardware USB built in.
[12:08:57] <Lambda_Auriga_> in which case, USB programming on for the AVR is not simple.
[12:09:41] <jaggzt> Lambda_Auriga_, well, I made a custom set of buttons for her.. and the switches just ran out to a separate mouse (wired to its buttons/switches).. but now I need to do something more advanced
[12:10:07] <jaggzt> Lambda_Auriga_, here's the button set:
https://www.flickr.com/photos/32284628@N05/16303375531/
[12:10:32] <jaggzt> it's upside down there. Here it's also upside down -- the 2 button version:
https://www.flickr.com/photos/32284628@N05/15245209364/
[12:10:55] <jaggzt> you can see that one on its stand
[12:11:07] <jaggzt> you grab it like a bicycle grip to use it
[12:11:26] <Lambda_Auriga_> I have a chord keyboard like that.
[12:11:40] <Lambda_Auriga_> it has a strap that goes around the hand though.
[12:12:09] <jaggzt> yeah, the 32u4 has usb built in.. partially why I got that one. Casper already referred me to .. what was it.. tinyusb library I think? for those mcu's that don't have it
[12:12:11] <Lambda_Auriga_> one hand...7 buttons...full keyboard.
[12:12:31] <jaggzt> sounds like you never use it though
[12:12:32] <Lambda_Auriga_> vusb is bitbanged usb for chips without hardware usb.
[12:12:46] <Lambda_Auriga_> for the 32u4 I would recommend LUFA
[12:12:49] <jaggzt> I've wondered about those chord keyboards for 15 years :)
[12:13:02] <Lambda_Auriga_> works great if you use it enough and learn it.
[12:13:26] <Lambda_Auriga_> I know someone who types with one while riding a recumbant bike.
[12:13:32] <Lambda_Auriga_> recumbent
[12:13:48] <Lambda_Auriga_> it's attached to the handlebar.
[12:14:00] <jaggzt> heh.. nice
[12:14:07] <Lambda_Auriga_> he is a writer and avid bike rider.
[12:14:12] <jaggzt> lol
[12:14:32] <Lambda_Auriga_> has a 10 inch tablet mounted so he can see it while he is riding.
[12:14:38] <jaggzt> what if I'm a writer and an avid contemplator?
[12:14:59] <jaggzt> and meditator?
[12:15:00] <Lambda_Auriga_> and the one hand keyboard for writing fiction or his experiences on the road.
[12:15:20] <Lambda_Auriga_> he tried google glass but found it too distracting.
[12:16:17] <Lambda_Auriga_> claims to do 40 to 60 words per minute, depending on traffic.
[12:16:32] <jaggzt> what city?
[12:16:47] <Lambda_Auriga_> he lives in kansas city but rides all over the country.
[12:17:01] <Lambda_Auriga_> a couple years ago he went on a tour of europe on bike
[12:17:06] <Lambda_Auriga_> and is planning on a china trip next.
[12:18:10] <jaggzt> :)
[12:18:30] <jaggzt> (why is atmel's bootloader closed source?)
[12:19:19] <Lambda_Auriga_> because they didn't release the source for it.
[12:19:31] <Lambda_Auriga_> there are dozens of bootloaders for atmel chips though.
[12:23:11] <jaggzt> yeah.. just doesn't seem like the kind of thing one would need to keep closed..
[12:23:13] <jaggzt> no biggie..
[12:23:22] <Lambda_Auriga_> happens all the time.
[12:23:37] <Lambda_Auriga_> many companies keep code for microcontrollers closed.
[12:24:06] <jaggzt> I need to find a way to incorporate more movement and exercise into my life
[12:24:17] <jaggzt> linus has his walking desk..
[12:24:26] <jaggzt> not sure if that's all that useful though
[12:28:12] <Lambda_Auriga_> I do like using voice recording then later speech to text processing for note taking.
[12:28:55] <jaggzt> really? that's cool..
[12:29:12] <jaggzt> I've never been comfortable talking alone to it.. I keep stopping.. thinking of my next phrase.. part of a phrase.. word
[12:29:12] <Lambda_Auriga_> just use my phone to do voice recording while I drive.
[12:29:23] <jaggzt> how do you .. just talk?
[12:29:28] <jaggzt> when talking to people I can talk fine
[12:29:39] <jaggzt> well, I wouldn't say fine.. but, I can sure talk a LOT :)
[12:29:50] <Lambda_Auriga_> I wear a bluetooth headset constantly and have a recorder I start with a touch of a button and just talk.
[12:29:55] <Lambda_Auriga_> I talk a lot too.
[12:30:07] <Lambda_Auriga_> more to myself than to humans around me.
[12:33:05] <Lambda_Auriga_> tacozagna for lunchies!
[12:34:27] <jaggz-a> I almost never talk out loud to myself... I should try.
[12:34:48] <jaggz-a> supposedly thinking is not as useful as people think it is...
[12:34:51] <Lambda_Auriga_> I do constantly.
[12:35:08] <Lambda_Auriga_> often times the only way for me to have an intelligent conversation.
[12:35:30] <jaggz-a> I don't understand
[12:35:40] <Lambda_Auriga_> I deal with a lot of idiots through the day.
[12:35:41] <jaggz-a> (kidding)
[12:35:58] <Lambda_Auriga_> I'm not.
[12:36:34] <jaggz-a> yeah, no, I was joking about not understanding you
[12:38:36] <jaggz-a> most people just don't seem to be aware... I believe it's partially limitations in capability, but LARGELY it's upbringing.
[12:39:13] <Lambda_Auriga_> the common sense gene is the rarest gene in the human genome.
[12:40:17] <jaggz-a> a geology prof in college brought out a good point: when you begin learning about the geological features, you'll see things you've never seen, though they have been there the whole time
[12:41:47] <jaggz-a> since people aren't usually raised in such a mentally nourishing environment, at many levels, they haven't developed the awareness
[12:43:00] <Lambda_Auriga_> I had a teacher in highschool who taught us how to think and how to learn before teaching us anything else.
[12:43:09] <jaggz-a> if they have the capability, and are young/plastic enough, it cam be developed still to a good degree.. under the right guidance (more helpful if the drive is there)
[12:43:44] <jaggz-a> that's awesome.. yeah.. learning how to learn is also really important
[12:44:05] <Lambda_Auriga_> I use the same methods,,or try to anyhow,,when working with kids these days.
[12:44:40] <Lambda_Auriga_> I teach electronics(mostly digital) and microcontrollers to kids in the 12 to 16 year old range as a side project for those who wish to learn during the summer.
[12:44:42] <jaggz-a> and then there's meditation, where one can reduce the logical processing of the brain, but even better use the resources.of the mind
[12:45:46] <jaggz-a> what types of techniques?
[12:46:22] <Lambda_Auriga_> make learning fun...make them think...teach them how to think for themselves..
[12:46:57] <Lambda_Auriga_> encourage them to actually think and not just regurgitate facts.
[12:47:56] <Lambda_Auriga_> encourage them to question everything...then help them find the answers to their questions without actually giving them the answers outright.
[12:49:09] <jaggz-a> awesome.. mostly people are taught to study existing "facts".
[12:49:39] <Lambda_Auriga_> bah
[12:49:44] <Lambda_Auriga_> facts you can look up.
[12:49:53] <jaggz-a> not even studying the discoverers' thoughts and writings..
[12:49:57] <Lambda_Auriga_> knowing how to look up said facts is the way to go.
[12:50:23] <Lambda_Auriga_> my chemistry and physics teacher would let us do open book tests..even midterms and finals were open book.
[12:50:33] <Lambda_Auriga_> we could use any resource in the room except for each other.
[12:51:00] <Lambda_Auriga_> one midterm I was stuck...couldn't find the answer in any books anywhere....so, I asked the teacher..and he showed me where to find it.
[12:51:37] <Lambda_Auriga_> pointed me at the right book anyhow...but that was enough.
[12:52:31] <jaggz-a> :)
[12:55:56] <vsync> googloids
[12:55:59] <vsync> ...awesome
[12:56:05] <Lambda_Auriga_> way pre-google.
[12:56:14] <jaggz-a> hemorrhoids?
[12:56:21] <Lambda_Auriga_> this was the same teacher who wouldn't let us use calculators
[12:56:29] <Lambda_Auriga_> but, he issued slide rules.
[12:56:33] <Lambda_Auriga_> and taught us how to use those.
[12:56:34] <jaggz-a> heh.. cool
[12:56:40] <Lambda_Auriga_> back in the 80s.
[12:56:43] <vsync> googloids nonetheless
[12:57:26] <jaggz-a> memorization is also undervalued generally.. at least in the education I was exposed to
[12:58:08] <Lambda_Auriga_> I find I remember things through use rather than just rote memorization.
[12:59:50] <jaggz-a> likewise.. which can be a problem with the abundance of projects and time between themm, for me
[13:00:24] <jaggz-a> but the visualization memorization techniques have a much longer retention
[13:01:29] <jaggz-a> http://www.ted.com/talks/joshua_foer_feats_of_memory_anyone_can_do?language=en
[13:20:26] <LeoNerd> Anyone played much with USI doing I2C? I'm trying to work out how to do software strobe
[13:22:13] <LeoNerd> Ahah! OK that's nontrivial but I think I've worked it out.
[13:22:46] <LeoNerd> In software strobe mode, pulsing the USICLK bit bumps the counter *and* moves the shift register. So you have to initialise the 4-bit counter to 8, rather than 0, to make it count up to overflow of 16 for sending 8 bits
[13:35:23] <LeoNerd> Mmm.. and I think I now have a shared I2C + SPI control using the USI
[13:35:39] <LeoNerd> The trick is just to move SCL to another GPIO pin and not use the USI's clock output for it
[14:26:41] <hetii> Hi :)
[17:34:14] <davor> hello
[17:34:35] <davor> are internal pullups still enabled even when a 328p is in power down mode?
[17:37:51] <Fleck> yes, only clock stops
[17:52:43] <davor> thanks Fleck
[17:57:54] <postmodern> I'm trying to compile the monochrome firmware with avr-libc 1.8.0, but I'm getting a compiler error
[17:59:41] <postmodern> http://pastebin.com/2dxr0KCp
[18:01:12] <Fleck> postmodern: shoe me /usr/avr/include/util/delay.h line 164 pleaser
[18:01:15] <Fleck> *please
[18:01:41] <vsync> shoe on head
[18:01:54] <Fleck> ehh
[18:01:59] <Fleck> sorry :D
[18:02:01] <postmodern> __builtin_avr_delay_cycles(__ticks_dc);
[18:02:02] <Fleck> *show
[18:02:27] <postmodern> https://images.encyclopediadramatica.se/f/fb/Place_shoe_on_head.jpg
[18:04:37] <Fleck> postmodern: can you disable optimization and try again?
[18:04:44] <Fleck> compile again
[18:05:25] <postmodern> only optimization is -Os
[18:07:26] <postmodern> with OPT disabled, a larger error:
http://pastebin.com/j0CpMxiQ
[18:08:45] <Fleck> avr-gcc --version ?
[18:09:47] <postmodern> (Fedora 4.9.2-1.fc20) 4.9.2
[18:10:38] <Fleck> can you try with 4.8.2 for example?
[18:12:07] <postmodern> hmm not sure, doesn't appear to be many avr-gcc versions for fedora
[18:16:27] <Jartza> postmodern: try adding #define __DELAY_BACKWARD_COMPATIBLE__ before #include <util/delay.h>
[18:16:59] <Fleck> or in makefile
[18:17:34] <Jartza> that too
[18:20:48] <postmodern> ah that got me further, now hitting regular C issues
[18:24:49] <postmodern> woot, adding const to read-only data fixed it
[18:25:23] <postmodern> am I correct in assuming they probably want 'const' instead of 'static' for global read-only variables?
[18:31:52] <Jartza> sure, that's what const means.
[18:32:58] <Jartza> static doesn't really make the variable "read only"
[18:33:05] <Fleck> yeah
[18:33:41] <Jartza> global static makes the global variable bound to file scope
[18:34:13] <Fleck> static is the most confused keyword IMO :D
[18:34:17] <Jartza> so other files can't access the variable using extern, but functions in file where the variable is defined can mess with it as much as they want
[18:34:42] <Jartza> Fleck: one of them, amongst const :)
[18:34:43] <postmodern> ah ha, static does respect file scope
[18:35:01] <postmodern> well i guess i should try uploading the new .hex file and see if my changes worked
[18:35:08] <postmodern> before I send a pull request that is
[18:39:45] <Fleck> Jartza: hmm, what's confusing about const?
[18:40:04] <Jartza> Fleck: depends where you use it. nothing, if you just have "regular" variables
[18:40:33] <Jartza> but people get confused about const placement when you have for example pointer to struct of pointers etc :)
[18:41:42] <Fleck> ghh
[18:43:05] <Jartza> and all of the combinations of those
[18:43:41] <Jartza> like constant pointer to writable variable or writable pointer to const variable or const pointer to const variable :)
[18:44:40] <Jartza> "int const * p" versus "int * const p" versus "int const * const p" can be confusing
[18:45:14] <Fleck> yeah
[18:46:06] <Jartza> and even more confusing is that "const int *p" and "int const *p" are the same thing :)
[19:01:00] <hackvana> Jartza:
http://www.cdecl.org/
[19:03:00] <Fleck> ;p
[19:17:53] <LeoNerd> GAHHH
[19:18:15] <LeoNerd> 2 hours hacking on my USI-based I2C code to hunt a bug, that turned out to be because my chip was running at 5V talking to a sensor at 3.3V
[19:18:26] <LeoNerd> It _almost_ works, but the odd bit here and there sometimes reads wrong
[19:24:53] <postmodern> holy cow it worked!
[19:25:07] <postmodern> although adafruit really should have used a better FTDI socket for the monochron kit
[19:25:21] <postmodern> really tedious holding the FTDI cable in place while typing with the other hand
[19:26:22] <Xark> postmodern: Agreed. :)
[19:31:30] <postmodern> hmm why does `avrdude -p atmega328p -P /dev/ttyUSB3 -b 57600 -c usbtiny -B 1 -U flash:w:monochron.hex` complain about /dev/ttyUSB3 not being of format usb:bus:device?
[19:31:45] <postmodern> but `avrdude -c arduino -p m328p -P /dev/ttyUSB3 -b 57600 -U flash:w:monochron.hex` works?
[19:36:25] <Lambda_Auriga_> because it has a bug in the error reporting?
[19:40:23] <postmodern> Lambda_Auriga_, i would expect a consistent error then
[19:40:30] <Lambda_Auriga_> naaa
[19:41:04] <Lambda_Auriga_> consistency in open source software?
[19:41:06] <postmodern> im guessing the difference in -p and -c are causing it?
[19:41:08] <Lambda_Auriga_> what world do you live in?
[19:41:22] <postmodern> Lambda_Auriga_, a deterministic one ;)
[19:45:34] <postmodern> yep it was -c usbtiny, -c arduino fixed it
[19:45:37] <postmodern> grumble open sores
[19:58:40] <Lambda_Auriga_> are you using a usbtiny or an arduino?
[20:03:10] <postmodern> Lambda_Auriga_, it's the monochron kit, which i believe uses an atmega328p
[20:03:37] <Lambda_Auriga_> never heard of it.
[20:03:47] <postmodern> https://learn.adafruit.com/monochron/
[20:04:03] <postmodern> fun little kit, good for getting your feet wet with AVR programming
[20:05:30] <Lambda_Auriga_> 80 bucks?!?!
[20:06:48] <postmodern> too much or too little?
[20:07:13] <Lambda_Auriga_> well, the avr on a board you can get as an ardweeny for around 10 dollars
[20:07:18] <Lambda_Auriga_> the display you can get for under 30.
[20:08:18] <Lambda_Auriga_> they are charging you a fortune for 15 dollars worth of power supply and components and the case.
[20:10:19] <postmodern> ouch, i guess your paying extra for the board and the custom enclosure
[20:11:58] <Lambda_Auriga_> pretty much.
[21:06:56] <Tom_itx> mmm did dean take his website down?
[21:07:11] <Tom_itx> abcminiuser_???
[21:07:19] <Lambda_Auriga_> the lufa site?
[21:07:28] <Tom_itx> i get not found..
[21:07:51] <Tom_itx> Sorry, the website www.fourwalledcubicle.com cannot be found
[21:07:59] <Lambda_Auriga_> same here.
[21:08:12] <Lambda_Auriga_> responds to pings.
[21:08:22] <Tom_itx> oh the horror!!
[21:08:33] <Lambda_Auriga_> http://fourwalledcubicle.com/
[21:08:41] <Lambda_Auriga_> he got rid of the www.
[21:08:46] <Xark> postmodern: I quite like the Monochron, but I wish the display was just a bit more responsive.
[21:08:57] <Lambda_Auriga_> something horky with the dns.
[21:09:17] <Tom_itx> still no go
[21:09:24] <postmodern> Xark, yeah, noticing minor flaws in the code here/there
[21:09:33] <Lambda_Auriga_> http://fourwalledcubicle.com/LUFA.php
[21:09:36] <Lambda_Auriga_> works from here.
[21:09:56] <Tom_itx> not here
[21:12:40] <Lambda_Auriga_> just emailed Dean about it.
[21:14:19] <Tom_itx> he's on here
[21:14:35] <Lambda_Auriga_> yeah, but, sometimes he might not watch the channel.
[21:14:42] <Lambda_Auriga_> I know I'm on here 24/7
[21:14:55] <Lambda_Auriga_> but don't always have access to my irc client.
[21:15:18] <Lambda_Auriga_> but I get email all day.
[21:15:42] <Lambda_Auriga_> hmmm..
[21:15:45] <Lambda_Auriga_> failure of the email.
[21:16:17] <Lambda_Auriga_> something seriously screwed up with his domain.
[21:16:20] <Lambda_Auriga_> or the server.
[21:17:17] <Lambda_Auriga_> fourwalledcubicle.com seems to use a mail relay and something happened with it as it is telling me to turn on smtp authentication to try to send to it....and I have smtp auth required for my email...
[21:25:20] <abcminiuser_> Wait what?
[21:25:22] <abcminiuser_> Works here
[21:25:33] <Lambda_Auriga_> having fits from here.
[21:26:38] <abcminiuser_> Expiration Date: 07-feb-2015
[21:26:39] <abcminiuser_> *&^%$*&^%(
[21:26:44] <Lambda_Auriga_> OOPS!
[21:27:01] <Lambda_Auriga_> seems it just hasn't fully propagated to everybody.
[21:28:16] <abcminiuser_> Every. Year.
[21:28:26] <abcminiuser_> I'll see if I can buy the domain off Angus
[21:28:30] <Lambda_Auriga_> I renew mine for 3 years at a time.
[21:29:08] <abcminiuser_> Angus very kindly provides server space and the domain, but every year I forget to poke him for renewals
[21:29:14] <abcminiuser_> I should see if I can buy the domain, but keep the hosting
[21:29:15] <Lambda_Auriga_> haha.
[21:29:37] <abcminiuser_> Anyway I own dean.camera, which is an alias
[21:29:46] <abcminiuser_> So anything hardcoded will be broken, but use that instead
[21:30:06] <Lambda_Auriga_> that works.
[21:30:24] <abcminiuser_> Crap, that means my primary email will bounce also
[21:30:29] <Lambda_Auriga_> yup.
[21:32:46] <abcminiuser_> Yay, no pressure to reply then
[21:33:02] <Lambda_Auriga_> hehe.
[21:33:23] <Lambda_Auriga_> I like it when work email goes down...hate it when it comes back up though.
